[STDS-802-16] [PREAMBLE] Preamble ad-hoc: Low complexity common synch sequence design

["Hosur, Srinath" <hosur@TI.COM>]

All,

We support the common synch symbol for the preamble design, since it
should help in acquisition time and reduce the mobile complexity and in
turn the power consumption.

The current and all the proposed sequence designs are based upon
exploiting the periodicity of the common synch symbol in time domain and
taking the differential
between successive symbols and then averaging over the differential for
the given synch symbol length. Given that the length of the common synch
symbol is N (N = 128, 512, 1024), then the mobile has to perform
~(N/3)*(2) complex multiplications and (N/3)*2 complex additions per
correlation output. Also, this output is to be calculated for every
shift of the ADC output during initial acquisition and over the window
of uncertainty during handoffs. During initial acquisition, this would
mean that the computations are done at a rate of 8 MHz. Even for N =
128, 512, 1024 this implies ~ 688 M, 2.73 G, 5.46 G complex multiplies
and adds per second. Assuming that a real add is four times lower in
complexity as compared to a real multiply, the complexity for an N/3
repetitive design would be: 2*(N/3)*(4*4+2)+2*(N/3)*2 equivalent adds.
This results in  ~ 13.7 G, 54.6 G and 109 G equivalent real adds per
second. We think that this could result in a lot of complexity and power
consumption for the mobile for intial acquisition.  The problem might be
somewhat alleviated during handoffs, depending on the uncertainty
window. So the common synch symbol design should focus on optimization
for the time domain correlation. The TI proposal posted on
http://temp.wirelessman.org/ reflector on 2nd August 2004 tries to
optimize the power consumption and complexity of the correlations for
acquisition. In this document, we propose a hierarchical common synch
symbol made up of repetitions of a basic sequence Z with different
phases - for eg. if Z is a sequence of length 16, then the common symbol
for a length 128 sequence is made up of 8 repetitions of Z with
different phases {Z,-Z,Z,Z,-Z....} (please see the document for the
exact nature  of the hierarchical sequence). We can thus see that the
proposed sequence/proposed sequence structure has an underlying
repetitive structure which allows frequency estimation error estimation
using partial correlations once timing acquisition is achieved at the
same time cutting down the correlator complexity. The hierarchical
design has the following advantages:

   1)      Only real additions and no complex multiplies resulting in
lower power and complexity for frame timing estimation.

   2)      Flexibility in allowing partial correlations for frequency
error estimation.

   3)      The structure preserves the repetitive property of the
current common synch symbol so a different receiver design can always be
used.

Complexity Analysis:

The hierarchical sequence of length N needs ~2*2*sqrt(N)  real adds per
correlation output. Thus the complexity for length N = 128, 512, 1024 is
384 M, 768 M, 1.024 G real adds per second. Thus, the hierarchical
design would contribute to complexity a reduction by ~ 35 x, 75 x and
105 x for N=128, 512, 1024 respectively compared to the current common
synch symbol acquisition complexity.

The acquisition procedure for the common synch symbol would then be,

(1) Do a coherent time domain correlation against the time domain
sequence
(2) After timing acquisition, use the partial correlations over the
sequence to get frequency error estimation

The secondary synch symbol to indicate the group of the SS can now be
either code multiplexed with the common synch symbol, the original TI
proposal gives such candidate secondary synch symbols. Alternatively it
can also be time multiplexed with the common synch symbol by
transmitting them in alternate frames. Thus this approach combines the
advantages of the common synch symbol and the group ID proposed by
Proxim, by transmitting both the common synch symbol and the BS group ID
symbol - for e.g. in alternate frames.

Srinath Hosur/Anand Dabak
Texas Instruments