[RPRWG] HW complexity (preemtion/cut through)
I recognized some comments/concerns regarding HW complexity in case of
preemtion or cut through.
I am convinced, either decision should be based upon known HW complexity
and performance issues.
Coding and synthesizing a series of FSMs, covering single traffic,
multiple class/priority traffic
with or without preemtion and/or cut through, one can demonstrate, that
additional complexity caused
by cut through or preemtion will/should not be an issue. This holds true
for FPGA as well as
CPLD architectures.
E.g.: A FSM for one priority consumes 4 logic blocks. A FSM for two
priorities, cut through with preemtion
consumes 25 logic blocks. E.g. Virtex-II (Xilinx) supports
SPI-4(2) interfaces with up to 10Gbit/s and
provides up to 15.000 logic blocks. Other families/vendors even
do more.
I will present my results in May.
Wolfram