| Thread Links | Date Links | ||||
|---|---|---|---|---|---|
| Thread Prev | Thread Next | Thread Index | Date Prev | Date Next | Date Index |
All, I will discuss our experience supporting the development of a 1 Meter 6G system. I will then describe how I would like backplane models characterized. The DesignCon presentation “Simulating Large Systems with Thousands of Serial Links” in session 8-WA3 can give you more details on the system. In order to simulate each of the channels, we needed to build 22 models for each channel. The following describes these models: 1. Tx and Rx Algorithmic and Analog model. 2. Tx and Rx package model for each pin of the package 3. The via models on the Tx, Rx and Backplane 4. The Trace models on the Tx, Rx and Backplane 5. The Connector models on both the Tx and Rx end of the channel 6. The blocking cap model We correlated each of these model with measurement. The overall system had channels ranging from 15” to 40”, multiple package interconnect lengths, multiple interconnect lengths on each board, multiple PCB materials, different connector rows and columns, vias with multiple depths and via stubs. Only 5% of the nets had low margins that depended on Tx and Rx process corner, specific pins, specific routing lengths, specific routing layers, specific connector rows and material properties. Developers of 892.3bj systems will require choosing Tx and Rx buffers, packages, board stackups and materials, routing rules, via geometries, blocking caps, and connectors. The developer will need to know the manufacturing variability of each of these pieces. Ultimately the developer will make tradeoffs between each of these choices to minimize system cost, and maximize system performance and yield. This should be a “firm grasp of the obvious”. The backplane via and traces need to be characterized to do the above analysis. Focusing first on the traces, the analysis requires a an S-Parameter model of the Traces between the backplane connector via. In the 6G system we found that a Wline model with a loss tangent and surface roughness was sufficient for 6G channels. Our correlations with measured data indicated that work needs to be done to predict accurate S-Parameter models for interconnect for 25G channels. At 12G Nyquist, we found variability between traces on the same board and the shape of the Insertion Loss per inch between boards, between board vendors, and between materials. My recommendation to this committee is that it defines a method that a board manufacturer can describe a nominal trace model with sufficient accuracy to enable a tool to generate accurate S-Parameter data. In addition, the board manufacturer should supply manufacturing variation data, preferable in the form of a Probability Distribution Function. One such form of the model might be a Dk, Df table as a function of frequency. Each board vendor would supply manufacturing variances on this data in the form of min and max masks, and deviation masks. Finally, my recommendation to this committee is that it defines a min, max and deviation masks for Dk and Df that will work on a 1 meter reach channel with reasonable choices for the daughter cards, connectors, and backplane vias. Walter Walter Katz Phone 303.449-2308 Mobile 720.333-1107 |