Hi All,
Just adding some more analysis data regarding the test channel return loss…
Extraction of short vias with ~15mil stub (4 in a row, 1mm pitch):
Concatenation of: viasè 105ohm trace èvias (Internal layer at the upper half of the board break-out) to get the following return loss:
One can see that, even the -12dB, is a bit hard to achieve and will require high board manufacturing control (impedance / stub length, etc.)
Taking into account that this is a 25Gbps/lane board one would expect it to be optimized and tightly controlled.
Best regards,
Liav
I had to remove the pictures from the former mail (below), because of a mail size limitation of the reflector.
Please refer to the former posted mail for the complete data.
Hi Charles and All,
First I want to specify that I support the incorporation of Comment #84 brought by Charles Moore, but would like to suggest slightly relaxing the test channel return loss requirement from 15dB to 12dB (HFSS extraction results and reasoning for suggesting a different value at the end of this mail).
I find the 15dB may not be feasible taking into account reasonable deviations from ideal design.
The comment:
The reasoning for the 15dB requirement: (As Charles shared with me)
• Return loss testing accuracy would be less influenced due to test fixture reflections.
Suggested altered value:
• Correct the “test fixture” trace max return loss requirement to 12dB (100M – 13GHz) due to the following reasoning and extraction results (a recommendation for 15dB to supply a better return loss measurement may be appropriate):
• One can expect to optimize the vias, choose the right material, minimize multiple reflections as much as possible on a test board.
• It is possible to get return loss of no-stub vias with a combined trace-via loss of 1.5dB to be ~-14dB (no multiple reflections were taken into account).
• A 12mil stub with a combined trace-via loss of 1.5dB is ~-13dB (no multiple reflections were taken into account)..
• Extra degradation seen due to multiple reflections between via (with no stub) and SMA/SMP – Analysis not provided in this Email.
• Minimal stub (4mil dielectric + 2.1mil PS copper) è trace è u-via resulted in -12.5dB – minimal expected multiple reflections.
HFSS extraction summary:
· “light” capacitance vias were used:
· Extraction result of a no-stub via. Incorporating a 105ohm trace (reasonable tolerance for sample boards) to get 1.5dB loss @Fb/2:
· Extraction results of the same vias, but with a 12mil stub (breaking out on PS-2) è max ret loss = -13dB. No multiple reflections were taken into account here.
· Extraction results – of a vias with a 4 mil stub è trace è u-via: Using a via to break-out to an internal layer adjacent to the print side. Route away using the internal layer and then connect to the PS with a u-via:
Best regards,
Liav