Colleagues, I am using the reflector to follow up on the discussion in last week’s ad hoc meeting (kochuparambil_3ck_adhoc_01_092221
slides 6-9). If the resulting discussion will be too heavy, I will move it to a separate thread with just the participants. You are welcome to respond privately if you’d like to be included.
To sum up my proposal (joint for comments 37 and 38):
- Use the linear pulse fit procedure and the
vf (as specified in 162.9.3.1.2, with the exception that Tx equalization is not turned off) as an additional protection from large host output signal;
this measurement is done with PRBS13Q (like all other C2M parameters) and the result is valid for any pattern.
- Specify the maximum
vf as 300 mV (comment #38)
- Alternatively, 450 mV (comment #37)
- Keep the differential peak to peak voltage specification and limit value.
- No change to module output specifications (may be aligned in the future if deemed necessary).
Comments #150 and #96 (on the same topic, but not related to
vf) can be resolved separately.
Here is the rationale for 300 mV:
- Module “short” output is limited to 0.6 V PtP after a low-loss channel; this corresponds to
vf of 300 mV.
- We should assume that the Tx has nonzero equalization (“pre-emphasis”) which will reduce the
vf, compared to the values specified for CR (with equalization off).
- The Tx FFE can be assumed to have DC gain no higher than 0.68 (-3.35 dB) (see 1 in “details” below the line). In practice, we see that stronger equalization is required
to improve the VEC so the DC gain will be even lower in most cases.
- Recent COM analysis of C2M host output (TP1a) assumes maximum launch value (corresponding to
vf without equalization) of 0.45 (see 2 in “details”)
- If the host output is launched from the assumed maximum of 0.45 V (creating 0.9 V PtP without equalization and host channel loss), with DC gain of 0.68 it will create
vf=0.45*0.68=306 mV.
- In a multi-port hosts (such as switches) channels can vary significantly (both package and PCB) and we should assume that Tx equalization is tuned specifically per
lane. If a specific lane has higher-than-usual voltage, it is possible to reduce it (or use appropriately scaled FFE) to meet the 300 mV limit.
If we don’t want to assume anything about the Tx equalizer, the maximum
vf can be set to 450 mV, corresponding to the maximum value used in COM analysis (and assumed in previous C2M annexes). However, it is unlikely that this will be seen by any module input in practice.
I would like to have the
highlighted text above as the basis for the response to both comments #37, #38. If there are concerns or questions, please reply to this thread, or privately to me.
</Adee>
Details:
- DC gain due to Tx equalization: Contributed analysis did not list the specific FFE setting that was used for each channel. However, some contributions from Ali Ghiasi
include optimized settings for module output (TP4); these are used as a proxy for the host output on similar channels.
- ghiasi_3ck_03a_0120 slide 12 suggests [0.04 -0.18 0.72 -0.04] (for module
output, one setting) è DC gain is 0.54
- ghiasi_3ck_adhoc_01_011321 slide 10,
ghiasi_3ck_adhoc_01a_042121 slide 10 module output: [0.04, -0.18, 0.78, 0] “long”
è 0.64 , [0.02, -0.16, 0.82, 0] “short”
è 0.68
Note that these do not have a c(-3) coefficients; but in practice, on host output it is available and will likely be nonzero (based on actual host optimization – this is required to meet VEC),
further reducing the DC gain.
- All recent analysis uses Av=0.415 as the minimum swing case; the maximum was supposed to be set in Ane; this parameter had inconsistent values.
The VEC and EH limits were set based on the minimum value (0.415) so it is possible to meet them with reduced output if necessary.
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