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I agree with Paul’s comments. I also re-read clause 87 to determine why the diagram shows the use of the “Clean clock” for the signal characterization in figure 87-3. The reason is that
figure 87-3 is only used to measure J2, J9 and VECP when the sinusoidal jitter input frequency is “well within the 4 MHz to 10times LB”. (ie it is intend to be at a frequency that the CDR in the Rx can’t track). We need to make sure that this aspect of
the test methodology is preserved in clause 95 (eg by referencing clause 87) when using this diagram. Mike Dudek
QLogic Corporation Director Signal Integrity 26650 Aliso Viejo Parkway Aliso Viejo CA 92656 949 389 6269 - office. Mike.Dudek@xxxxxxxxxx From: Kolesar, Paul [mailto:PKOLESAR@xxxxxxxxxxxxx]
Jonathan, Thanks for your agile on-the-fly edits during yesterday’s call. The new diagram seems to reflect what we agreed during that call. I’ve just a couple touch-ups
to suggest. 1.
The “Symbol error ratio” and “Bit error ratio” test outputs should be presented with equivalent appearance. Specifically, they should both be shown
within boxes or without boxes. My interpretation of the other boxes is that each represents a hardware entity. However, these test outputs do not. Therefore I recommend removal of the box around “Bit error ratio”. 2.
The format of arrow pointing to “Symbol error ratio” is unlike all others. Unless there is a good reason for this distinction, I’d recommend making
it the same as the others. Regards, Paul
From: Jonathan King [mailto:jonathan.king@xxxxxxxxxxx]
Dear all Following today’s MMF ad hoc review of the Stressed receiver conformance test diagram which will go into clause 95, here is an updated figure, implementing all
the changes we’d agreed to during the call. The last slide is the crudely edited diagram we ended up with by the end of the call today, the first slide is the cleaned up version. Please let me know
Thank you all for your participation this morning ! Best wishes jonathan |