RE: [10GBASE-T] PAR and 5 critters
Vivek- I'm writing this from traffic so I'll be brief. The 6x is based on ops counts of our efficient realization vs. 1 TOP for a quad 1000BASE--T reported in both BRCM and Cicada press releases
-----Original Message-----
From: "vivek@cicada-semi.com"<vivek@cicada-semi.com>
Sent: 7/30/03 6:31:32 PM
To: "gzimmerman@solarflare.com"<gzimmerman@solarflare.com>
Cc: "stds-802-3-10gbt@ieee.org"<stds-802-3-10gbt@ieee.org>
Subject: RE: [10GBASE-T] PAR and 5 critters
George,
Can you walk me through the reduction in complexity from 45x to 6x. I'm
just talking about the cancelers here (Echo and NEXT). You don't have to
disclose any IP. Just a broad reference to the technique will do. I just
want to make sure that you're not double-counting any DSP techniques that
are already being used to reduce the complexity in today's 1000BASE-T
PHYs.
Regards,
Vivek
Cicada Semiconductor
>
> In deference to some of Brad & Bob Grow's earlier admonition, technical
> feasibility is a matter of increasing confidence as time moves on. The
> tone of this discussion appears to have moved from the "can't be done at
> all" to "how much & what kind of silicon will it require". I will assume
> that we have entered that stage.
>
> We have presented our estimates of feasibility at about 6X 1000 BASE-T
> and implementable in today's CMOS at the tutorial in November.
> Regardless, there is no doubt that 90nm will be a commercial processes
> well before 10GBASE-T is through the standards process (at the earliest
> 2nd half of 2005), and 65nm will be commercial as 10GBASE-T begins to
> ramp in the subsequent years.
>
> In direct response to Dan's concern, there are a variety of algorithms
> that do not require closing the loop at the baud rate, (the simplest of
> which are the look-ahead algorithms which have obvious complexity
> drawbacks), various reduced-state and lower-complexity forms are well
> studied in the literature, and have been implemented in commercial
> products. (Dan - you will also see EMI measurements from November)
>
> In deference to earlier comments by Vivek & others, yes, if I just take
> the simplest form of design (direct-form FIR) and multiply up by the
> baud rate & # of taps I get a huge complexity multipler (something like
> the 45X 1000 BASE-T), but just because the simplest-extension yields a
> huge complexity doesn't mean that it is non-feasible. Current art in
> efficient and multi-rate filtering algorithms don't scale linearly as
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