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Hello all,
Following the discussion regarding power, it looks like there is a consensus that the 10Gb Phy dissipated power will be very high at first silicon and relatively high at advanced future versions.
The average power is important for most problematic topics, such as thermal conditions, power source availability and so on.
The average power can be reduced by using the Power-Down mode. The transceiver does not transmit or receive data during significant periods of time. Instead of transmitting idle symbols while consuming full power, the system can enter the Power-Down mode. The transmitter power can be reduced by stopping the transmission, the receiver power can be reduced as only minimal receive functions will be active. The overall dissipated power during the Power-Done can be reduced significantly.
Of course there are algorithmic issues to solve, such as how to maintain the synchronization during the Power-Down mode, but these are technical problems that can be discussed and solved.
The average power with implemented Power Down mode depends on the length of idle periods.
The desktop/laptop PC transmits idles most of the time ( > 90% ?). I don’t know what happens in data centers.
.If we can reduce even half of the dissipated power by the Power Down mode, it is worth to be considered.
Regards,
Boris Fakterman - Intel Communications Group, Israel
Tel: 972-4-865-6470, Fax: 972-4-865-5999
mailto:boris.fakterman@intel.com