RE: [10GBASE-T] latency
Hi Stephen,
The latency requirements in the standard are based on clause 44.3 (which
refers to clause 31 and annex 31B). Underlying reason for specifying
delay budgets is "Predictable operation of the MAC Control PAUSE
operation" as the standard puts it.
In the 802.3ae days, there was a minor discussion in 2001 around the
latency budgets summed up in table 44.2 "Round-trip delay constraints".
Back then, I commented against the latency numbers of draft 3.0 (which
are now in the standard).
My argument back then was based on two points: a) the fact that the
individual delay numbers in table 44.2 seemed to be built assuming
different semiconductor technologies, and b) the fact that cabling delay
is several orders of magnitude above sublayer delay anyway if we look at
the distance objectives of the optical PHYs. For the sake of economic
feasibility, I proposed relaxing the numbers, but without success.
The current situation seems as if the delay budget threatens to inhibit
technically attractive solutions. What we are probably missing (today as
well as back then) is some data on the MAC control PAUSE operation and
how it is really used in the field. That could tell us how reasonable it
may be to add some slack to the current numbers.
Some data, anyone?
Best regards,
Mario.
-----Original Message-----
From: owner-stds-802-3-10gbt@majordomo.ieee.org
[mailto:owner-stds-802-3-10gbt@majordomo.ieee.org] On Behalf Of Stephen
Bates
Sent: Donnerstag, 19. Februar 2004 18:56
To: Booth, Bradley; stds-802-3-10gbt@ieee.org
Subject: Re: [10GBASE-T] latency
Hi Brad and the 10GBASE-T Group
I used to work for Massana (now part of Agere) but am now an Assistant
Prof at the University of Alberta. I've been talking to some of you
about this latency issue as I think it has a huge bearing on the
viability of 10GBASE-T.
I did some work based on the presentation of Scott Powell and others
that tried to estimate the power consumption of 10GBASE-T components.
Based on present performance criteria and ADCs featuring in ISSCC this
year I concur with his results which show that they are, by far, the
dominant power drain. For this and other reasons I am coming to the
conclusion that the trade off between the SNR target at the decoder
input and coding gain is not appropriate at present (I assuming we are
using the 1000BASE-T code).
Part of my research is involved with coding and decoding in high-speed
systems with ISI. One area of application is obviously 10GBASE-T. I know
Sailesh presented some work on LDPC codes. Another coding option people
have mentioned is a concatenated code. Both of these require that the
latency budget in 10G be relaxed. In the first case because LDPC
requires an iterative decoder and the second since we must interleave
between the two codes.
I have heard the figure of 1us being the limit for MAC to MAC latency in
10G though I've not heard any justification or reasons for this. Even
assuming we can 50% of this in the decoder we still only have about
400-500 baud periods (and hence clock cycles) to play with. This is a
very small figure for both the options above.
I think getting a better idea of what the upper bound on latency needs
to be is very important and I would be interested in hearing people's
opinion on the coding options for 10GBASE-T. I hope to make another of
the study group meetings as soon as my teaching commitments are
concluded.
If anyone has any questions about this please feel free to contact me.
Regards
Stephen
On Wed, 2004-02-18 at 12:12, Booth, Bradley wrote:
> I remember Sailesh mentioning that if we are willing to make
> trade-offs against latency, that we can make use of significantly more
> powerful techniques to reduce the complexity. I know people have been
> looking at this as a possible issue. What is an acceptable latency
> trade-off? Is the current latency requirement for 1000BASE-T creating
> problems for it in latency sensitive applications?
>
> Any thoughts or comments?
>
> Cheers,
> Brad
>
> Bradley Booth
> Chair, IEEE 802.3 10GBASE-T Study Group
> bbooth@ieee.org
> 512-732-3924 (W)
> 512-422-6708 (C)
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Dr. Stephen Bates
Dept. of Electrical and Computer Engineering Phone: +1 780 492 2691
The University of Alberta Fax: +1 780 492 1811
Edmonton www.ece.ualberta.ca/~sbates
Canada, T6G 2V4 stephen.bates@ece.ualberta.ca
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