Re: [8023-10GEPON] Revised 10G budget
Dear Dr. Effenberger,
I apologize for my late response because of my business trip last week.
As for the FEC codes, I thought RS-codes are the realistic FEC code option
regarding the balance of circuit size, signal processing, and FEC gain,
which was discussed in the Dr. Jeff Mandins material; 3av_0709_mandin_2.pdf.
I would also like to know the opinions from other chip suppliers.
I agree with you that, if the additional statement indicates the E-FEC gain,
it makes sense, and also, it should not necessarily be RS(255,223).
Let us pitch the ball to FEC-code specialists.
I personally think there could be another possible Power Budget option based
on S-FEC, which Dr. Mandin has suggested, or I should define 'FEC gain of
3-dB for PINs and 4-dB for APDs'.
Attached please find the Power Budget list based on the S-FEC.
Best regards,
Hiroshi Hamano
%% Frank Effenberger <feffenberger@HUAWEI.COM>
%% Re: [8023-10GEPON] Revised 10G budget
%% Tue, 23 Oct 2007 10:28:54 -0400
> Dear All,
>
> Whether the "FEC gain text" is enacted in a separate motion, or as part of the same motion as the optical baseline, is not a problem for me.
>
> I offered these words as a way to assuage the members who had such concerns. It is my hope that Hamano-san and Takizawa-san can provide us their feedback, so that we can better serve their needs and gain their support.
>
> Sincerely,
> Frank Effenberger
>
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HIROSHI HAMANO Network Systems Labs.
FUJITSU Labs. Ltd., Kawasaki, 211-8588 JAPAN
TEL: +81-44-754-2641 FAX: +81-44-754-2640
E-mail: hhlsi@flab.fujitsu.co.jp
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SFEC Power Budget.pdf