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All, Here is a slight revision, with the timing
of the block transfers from the PMA and to the descrambler made even more
explicit. Thanks to Jeff for suggesting that we make
the transfers synchronous to the XGMII clock. Sincerely, Frank E. From: Marek
Hajduczenia [mailto:marek_haj@xxxxxxx] Hi Frank, the changes look good. Are we going to discuss this on Thursday ? Regards Marek From: All, Attached is a document that has the small changes that try
to address the issues raised in the meeting yesterday. The key items are: 1) The bug
wherein the Append_Inbuffer function could get messed up by bit errors has been
fixed. The IF statement now operates by looking at the sh_cnt variable,
which is immune to received errors. 2) Gearbox
doesn’t exist problem ? The revised text gets rid of references to this object
that doesn’t exist. It gives a description of a “conceptual model”
wherein the 16 bit bus from the PMA is first serialized, and then deserialized
to a 66 bit wide bus. It leaves the option open to implement it in a different
way, but it does make the explicit requirement that a 66bit block is produced
every 6.4ns. I think that this covers the outstanding issues. If I
missed something or you have questions, please respond to me, so we can fine
tune this off line, and not consume valuable meeting time. Sincerely, Dr. Frank J. Effenberger 弗兰克 埃芬博格 Huawei Technologies Cell (908) 670 3889 Office/Home (732) 625 3001 |
Attachment:
3av_0809_Effenberger_1a.doc
Description: MS-Word document