Re: [10GMMF] TP3 Meeting minutes, November 23rd

[Tom Lindsay <tom.lindsay@xxxxxxxxxxxx>]

Mike et al -

 

What has changed my view is realization that the noise we are adding in the TP3 tester to emulate RIN (and modal noise, but that's separate from this discussion) adds as much random jitter (RJ) as I would expect from all sources from a transmitter at TP2. I missed this before. I would also expect that the pattern generator clock would add a bit more RJ, and the clock, pattern generator, and other elements may naturally add a small and appropriate amount of uncorrelated high probability jitter. I am not concerned about TP2 DDJ, because I expect we'll adequately take care of that with the ISI generators, as they will emulate the combination of TP2 and channel.

 

I don't completely have my arms around this, but given what I see at this point, there will be enough jitter already in the tester and no more is required. I agree with Piers that we may want some narrative words around this. I'm also trying to interpret what this means for TP2 specs to assure that TP2 is appropriately aligned with TP3 test conditions. But, I believe, at this time, we can move forward for TP3.

 

Thanks, Tom

tom.lindsay@clariphy.com
phone: (425) 608-0209
cell: (206) 790-3240

 

 

----- Original Message -----

From: Piers Dawe

To: STDS-802-3-10GMMF@listserv.ieee.org

Sent: Friday, November 26, 2004 6:24 AM

Subject: Re: [10GMMF] TP3 Meeting minutes, November 23rd

re:
>         ACTION: Tom and Piers agreed to work towards closing
> off jitter on our Nov 30 call
...
>         4. TP3 Jitter testing   Tom L.
...
> Tom and Piers still working on pk-pk UI figure for high
> frequency test.

We have made progress.  We agree that most jitter is of kinds that we (in LRM) should not emulate by high probability Tx clock jitter.  We get different answers from different calculation methods.  Mandating an extremely small amount of SJ seems like complexity for little benefit.  We are now trying to choose between no added jitter and 0.05 UIpp.

An in-between approach that I haven't yet discussed with Tom would be to state in the narrative the RMS jitter we might expect a tester's clock to have (say ~2 ps RMS), and say that if a tester has an exceptionally good clock, one can consider dithering it.  This might improve consistency between testers.

Piers