Re: [10GMMF] TP3: Request for suggested stressor levels
Title: Message
Hi
Petar,
I
would like to thank you for rising those issues. I fully agree with you that
actual EDC tested prototypes, behave somehow rudimentary with partial
coverage of lab-like testing situations. GiorgiaTech made a lot of nice work in
simulating finite length EDC performances differences respect ideal infinite
length models. The result was that according even to slight variation some
(Gaussian-like) IPRs the "implementation penalty" can vary between 2dB and 6dB
or even more. This must be accounted for in the stressor definition. In
addition, the undefined "implementation penalty" would be quantified into
several components, like finite length, noise enhancements, IC
technology bandwidth limitations, enhanced jitter and related CDR
requirements and penalties. Deterministic jitter out of every FFE+DFE block is
strongly enhanced respect the usual values accepted by standard CDR. As you
told, the system as whole must be included in the design prescription, not only
the EDC or the fiber. How would be the impact of EDC on CDR requirements? Would
we add CDR implementation penalties when it is used in a EDC based transmission
system? I guess this question would be addressed
carefully.
Thank
you for this contribution,
best
regards
Stefano
Jim (and the
rest),
I would like to suggest
that we first agree on criteria that the proposals should meet. All proposals
should include description what the test is stressing and how it would work
for a broad class of EDC chips. I strongly believe that in this process of
developing the standard, we have thoroughly investigated the channel and used
advanced models (that were made available to the standard in various forms) to
include degradations originating in the optical portion of the link. While
doing that, we argued about percentages and statistics, while in the meantime
we have heard very little about the EDC models. The performance of the entire
link depends on ALL components, and hence, there is little benefit into going
into very detailed channel models, without using models for the rest of the
link components that give the same level of accuracy as the fiber model. At
the end, the overall accuracy will be determined by the least accurate
component model.
Based on my
limited experience with EDC chips, I believe that the current EDC chip models
are rudimentary (I would compare them to a Gaussian approximation for the MMF
impulse response) and that the standard can not develop the stressor levels
with confidence without better models. I would only commend Clariphy (Norm and
Tom) for coming forward with a model that is one step forward towards our goal
of a robust and cost effective standard. However, I would like to stress that
this is only the first step, and we need more openness from the EDC vendors.
In particular, I would like to see the now unnamed implementation penalties be
assigned names and have models that address them. Those models should also
address the interdependence with the rest of the penalties that we have so far
taken into account (and that we just added). What I say is that the total of
the all implementation penalties in magnitude may be OK, but their
individual distribution may need some tweaking.
Without better knowledge what the EDC degradations are,
and what parameters affect them, we can't develop cost effective stress
tests and there will always be the danger that something slips through the
tests that should not.
So, I
believe that we have to discuss these issues first, and then it will be easy
to determine the stressor levels.
Regards,
Peter
P.S. I understand the desire of the EDC
chip vendors to protect their IP. However, I think that at this point we do
not have the sufficient level of details to develop the necessary stressor
levels.
Petar
Pepeljugoski
IBM Research
P.O.Box 218 (mail)
1101 Kitchawan Road,
Rte. 134 (shipping)
Yorktown Heights, NY 10598
e-mail:
petarp@us.ibm.com
phone: (914)-945-3761
fax:
(914)-945-4134
Jim McVey
<jim.mcvey@FINISAR.COM>
Sent by: owner-stds-802-3-10gmmf@IEEE.ORG
03/22/2005 06:34 PM
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Subject
| [10GMMF] TP3: Request
for suggested stressor levels |
|
Hello TP3 Members,
Per our teleconference today (Tuesday
March 22), I am soliciting inputs for the TP3 stressor level. This
stress level should be consistent with the goal of practical implementation at
reasonable cost and power.
Please include the rational for your
suggestion.
I will summarize the suggestions identifying them as
"Suggestion A", "Suggestion B", etc. with no mention of names. My goal
is to publish this summary by close of business Thursday, March 24,
2005.
As discussed in the call, this solicitation is aimed at getting
full input from the EDC manufacturers, but suggested values from any
interested party are encouraged as well.
Please send your comments
to:
jim.mcvey@finisar.com
Thank you very much,
- Jim
McVey
+ 1 650 740 7732