RE: Give me serial 10GbE or.......
Joe, Pat, Richard and All:
Usually the implementation issues are left for each company to optimize its
design to achieve the most cost-effective goal, which is part of the
incentive for competing in the marketplace to "make it even better, and
cost-effective than others". The market will determine the most
cost-effective approach and products. Our job is to provide market the
opportunities to prosper, while we are setting standard for
"interoperability", but not to interfere the market dynamics. I believe
this is always the goals for all standards, and HSSG is no exception.
Therefore, we should ask ourselves, what is HARI's role in this hot debate?
1. Should we introduce HARI to everyone as a tool for those need help,
without any binding?
2. Should we introduce HARI to market as an industry supported approach, but
not a standard, as GBIC, 10-bit Interfaces in early days?
3. Should we introduce HARI as a part of the IEEE 802.3ae standard, because
it is crystal clear that standard can not be completed without it?
As a component user, I need the interoperability to have multiple vendors
with competitive prices and services, but I also need the freedom to
innovate the products.
I believe we all have the obligation to the committee to carefully evaluate
and understand the issues, then vote correctly for the objective of our
committee.
For the time being, I like to be well informed through discussions and
laboratory data to prepare for my vote.
Regards,
Ed Chang
NetWorth Technologies, Inc.
EChang@xxxxxxxxxxxxxxxx
-----Original Message-----
From: owner-stds-802-3-hssg@xxxxxxxx
[mailto:owner-stds-802-3-hssg@xxxxxxxx]On Behalf Of Joel Goergen
Sent: Friday, December 03, 1999 7:26 AM
To: HSSG
Subject: Re: Give me serial 10GbE or.......
Pat,
A thread off of Rich's response ......
> > >c) The ability to use common PCB material to to build 10 Gbps products;
> >
> > -------------------------------------------------------------
> > No problem. If we obey the "short is good" rule of RF
> > and microwave layout, runs of 1-2 inches can be accomodated
> > between the transceiver and the ASICs. If one makes use of
> > buried stripline and blind vias, one extends this a bit further
> > without difficulty. FR-4 will support this just fine.
> > -------------------------------------------------------------
>
> I'm out of my league here. I'll leave this to the Ron Miller's, Joel
Goergen's,
> Michael Fogg's, Rich Feldmen's, etc. for comment.
I just don't know, here. I have thought about this alot and I am thinking,
if we head
in this direction, that I/we should come up with a test card with the
purpose of
evaluating the contribution of the '2 inch' or 'x inch' 10gig fr-4 segment
from a xcvr
to a phy in the jitter budget. My feeling at this point is that fr-4,
excuse me, that
the geometry and construction of an fr-4 model will yield significant Dj and
ISI
contribution where during the gigabit times, this was some what small and
easy to
slide into the T1 or T4 portions - more or less ignoring it.
I will admit that I understand the effects of 8b10b over geometry, but I
know not what
some of the new enc/dec concepts will look like - and I need to examine this
in the
lab before I could offer any more input on possible jitter contributions.
I think we may have to add a column or two in the jitter budget for the
board, but I
just don't know. Something along the lines of what Rich discussed in the
presentation
he gave in Kauia.
Take care
Joel