Re: Specific PMD support of XAUI/XGXS
Roy,
XAUI/XGXS is proposed as an optional interface between the RS and PCS. In the
P802.3ae Layer Model proposed by Mr. Brad Booth in Albuquerque:
http://grouper.ieee.org/groups/802/3/ae/public/mar00/booth_1_0300.pdf, slide 10,
both the optional XGMII and XGXS/XAUI interfaces/sublayers are shown.
I called Mr. Jaime Kardontchik's PAM5/4WDM proposal a PMD. I could have called
it a PMD/PMA/PCS. If I confused you or anyone else I apologize.
Best Regards,
Rich
--
Roy Bynum wrote:
>
> Rich,
>
> It was my understanding that XAUI was to be an optional XGMII physical
> distance extender, not an additonal sublayer between the PMA and the PMD.
> If it is an optional physical distance extender, then it would go inside the
> XGMII, between the RS and the PCS. XAUI would have nothing to do with PMD
> independence.
>
> Am I getting confused again? Is XAUI now something else?
>
> Thank you,
> Roy Bynum
>
> ----- Original Message -----
> From: Rich Taborek <rtaborek@xxxxxxxxxxx>
> To: HSSG <stds-802-3-hssg@xxxxxxxx>
> Sent: Friday, March 17, 2000 6:41 PM
> Subject: Re: Specific PMD support of XAUI/XGXS
>
> >
> > Jaime,
> >
> > It was a simple question. I'll try again:
> >
> > XAUI/XGXS addresses PMD independence, implementation flexibility, and
> > signal integrity by separating the intra-enclosure jitter domain from the
> > inter-enclosure jitter domain. At 10 Gbps, from the Reconciliation
> > Sublayer, signals and clocks cannot travel more than several inches
> > across proposed interfaces like the XGMII. XAUI/XGXS extends this
> > distance (maybe that's where the word "extender" relates to).
> >
> > So the question is: Is your PAM5/4WDM proposal compatible with the
> > proposed XAUI/XGXS?
> >
> > If the answer to the above question is NO. Then: Are you proposing your
> > own XGMII extender which is specific to only your PAM5/4WDM proposal?
> >
> > I'm only asking this because you do say in your original note that you are
> > "very open and flexible with respect to supporting /A/,/K/, etc.."
> >
> > Best Regards,
> > Rich
> >
> > --
> >
> > Jaime Kardontchik wrote:
> > >
> > > Rich Taborek wrote:
> > >
> > > > Jamie,
> > > >
> > > > Are you saying that your PAM5/4WDM proposal will not be compatible
> > > > with XAUI/XGXS? Please clarify.
> > > >
> > > > Best Regards,
> > > > Rich
> > > >
> > > > --
> > >
> > > Rich,
> > >
> > > Please, do not put in my mouth things that I did not say.
> > > I repeat below what I said before and I leave to others
> > > to fight the XAUI/XGXS/etc wars:
> > >
> > > >
> > > > I am very open and flexible with respect to supporting /A/,/K/, etc..
> > > > However, I would like to point out that these are completely
> > > > unnecessary in my proposal "PAM-5 4-WDM at 1.25 Gbaud".
> > > >
> > > > Jaime
> > >
> > > Jaime E. Kardontchik
> > > Micro Linear
> > > San Jose, CA 95131
> > >
> > > >
> > > >
> > > > Jaime Kardontchik wrote:
> > > > >
> > > > > Rich Taborek wrote on Friday 00:26, March 17:
> > > > >
> > > > > >
> > > > > > .............. A WWDM or Parallel Optics PMD
> > > > > > requires its PCS to support /A/, /K/, and /R/ to perform
> synchronization,
> > > > > > deskew, alignment and clock tolerance compensation. This
> information
> > > > > > must indeed be transported out through the PMD to enable the
> remote
> > > > > > PCS receiver to perform all of the latter functions.
> > > > >
> > > > > Rich,
> > > > >
> > > > > I am very open and flexible with respect to supporting /A/,/K/,
> etc..
> > > > > However, I would like to point out that these are completely
> > > > > unnecessary in my proposal "PAM-5 4-WDM at 1.25 Gbaud".
> > > > >
> > > > > I do follow exactly the same synchronization steps that you
> > > > > mention in Albuquerque's presentation, slide # 15:
> > > > >
> > > > > "4-lane link synchronization is a 5 step process
> > > > > 1-4 acquire sync on all 4 lanes individually
> > > > > 5 align/deskew synchronized lanes "
> > > > >
> > > > > Since I use the 1000BASE-T PCS instead of the 1000BASE-X
> > > > > PCS (8b/10b), the only difference is that each lane has its
> > > > > own 1000BASE-T PCS clocked at 312.5 MHz (instead of the
> > > > > 8b/10b coder) and a SERDES clocked at 1.25 GHz (instead
> > > > > of 3.125 GHz).
> > > > >
> > > > > The SERDES takes the four PAM-5 symbols generated by
> > > > > the 1000BASE-T PCS every 312.5 MHz clock cycle and
> > > > > delivers them serially to the PMD. Byte sync at the receiver
> > > > > is performed using the IDLE properties of the 1000BASE-T
> > > > > PCS. Lane alignment is trivial once you performed byte
> > > > > sync on the individual lanes.
> > > > >
> > > > > Jaime
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Richard Taborek Sr. Phone: 408-845-6102
Chief Technology Officer Cell: 408-832-3957
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