Re: 64/66 control code mapping
Mike,
> I'd like to make a couple comments on your note below:
> Regarding horizontal eye opening, serdes jitter tolerance
> is more a function of the PERCENTAGE eye opening rather
> than the absolute amount in picoseconds.
I don't see it this way from my comparisons of vendor data sheets.
> What isn't shown (and can't be) in those eye diagrams is the
> relative difficulty of the receiver's job. Run lengths are
> a huge factor here.
I don't disagree. And I think Shimon ( I know I screwed up the spelling ) asked
the question at the end of the presentation that he would like to see the effects
the receiver has to deal with. I have not had time to go to serdes vendors and
ask them for help - though TI, ME and Agilent have offered suggestions and
input. We have to look at this, but I am told at the moment it is not a
'stopper'.
> Second, I want to take exception to your statement: "Once we
> reach the long PCB trace, it is clear that 8b/10b has fallen
> off of a cliff." The 60% eye opening shown is well within
> receiver capabilities. Specifications require them to work
> down to 30 or 35% eye opening. Also, the presentation,
> http://grouper.ieee.org/groups/802/3/ae/public/nov99/jenkins_1_1199
> shows hardware results for virtually the same physical case.
> The eye after 20 inches is beautifully open due some simple
> pre-emphasis. I just don't see the cliff (at least, nowhere
> nearby).
Are you making the assumption that the high speed trace will be a perfect
geometry, or that it will be given absolute priority over everything else on the
board. If you are, then the cliff won't be there. And you are correct, anyone
familar with wave guides can help compensate the eye - or it can be done in the
chip. But if you consider the high speed stuff might get treated second, third
or tenth, then the picture changes a quite alot.
> I'm not arguing against any aspect of 64/66 code here. My
> only point is that serial data transmission with 8b/10b code
> is a well-developed technique in the toolbox of a large and
> growing number of vendors. In my opinion it is a low-risk
> plan for moving 3+ Gb/s across 20-something inches of PCB.
I really don't disagree with you. And if there was a way to keep 8B10B without
the over-speed, sign me up. But the 64/66 and scrambling methods give the slower
speed, have less spectral content to deal with, and allow more channel
attenuation. Yup - I know, they also require people to work hard and quickly to
demonstrate the technical feasability.
Take care
Joel Goergen