Re: 16-bit 625Mbaud XGMII
JR Rivers wrote:
>
> D.C.-
>
> For uncabled systems, the reduced range link works well, avoiding the 2.4V
> common mode input range requirement. Also, creative circuit designers may
> be able to figure out ways to use CMOS current steered circuits to generate
> the outputs, thus increasing fidelity and decreasing IC dynamic power
> requirements.
Alas, too many of the proposed standards require the full CM range.
Even the reduced range takes the CM value too high for thin-oxide
MOS devices. As for the "creative circuit designer," -- I are one.
The problem has more to do with the physics of advanced devices and
their intolerance of gate stress. (And is more severe at the receiver
than at the transmitter.)
Enough self-pity though -- this one is water under the bridge.
> At 08:45 AM 3/29/00 -0800, Bill Woodruff wrote:
> >
> >Gee, Who likes LVDS?
> >
> >I hate to hop into the middle of this, but LVDS became the 'standard' in the
> >telecom space for a very specific reason. Back in 1998, anyone wanting to
> >do a CMOS device with the x16 622MHz Interface faced a limited choice of
> >chip vendors. IBM is one of the best, and they had the LVDS available.
> >
> >At this time, GiGA was not a provider of such CMOS parts, but we were
> >shipping 10G PHY parts, so we got into LVDS interface discussions with most
> >everyone.
> >
> >LVDS is not a friendly interface for current switched logic families, but us
> >PHY folks using bipolar technologies have adapted.
> >
> >Meanwhile, LVDS has been codified in the OIF interface, and has become an
> >industry standard.
> >
> >Of course, a 2.5V Vcm is both obnoxious and unnecessary for this very short
> >point to point interconnect.
> >
> >However if the chip has a serial I/O on it, it is best if the low speed
> >interfaces are differential. I understand single ended I/O work well for
> >balanced codes in the 1Gb/s range, but a chip that worries about each ps of
> >jitter should not have 16 (or more) lines banging all ones or all zeros on
> >the low speed side. Even if you get it right the first time, some board
> >designer at a later date will take a shortcut and ground bounce will creep in.
> >
> >Bill
> >
> >Bill Woodruff ph: 805 496-7181 x14
> >GiGA North America Inc. fax: 805 496-7507
> >299 W. Hillcrest Dr., Suite 106 woodruff@xxxxxxxxxxx
> >Thousand Oaks, CA 91360 http://www.giga.dk/
> >
> >
> > >> JR Rivers wrote:
> > >> >
> > >> > How about 1.25 Gbaud LVDS?
> >
> > >> On the one hand, the telecom sector is going to LVDS in a very
> > >> big way. Which means that all of those spiffy medium-interface
> > >> suppliers will be happy with it.
> >
> > >> On the other hand, LVDS is utterly horrid for CMOS. Locking
> > >> in a 2.4v common-mode range for as far as the eye can see is
> > >> a death sentence for I/O performance scaling.
> >
> > >> > At 03:07 PM 3/20/00 -0800, Andreas Bechtolsheim wrote:
> > >> >
> > >> > >Jaimie: you need to count package pins, not signal I/Os.
> > >> > >
> > >> > >Your 625 MHz XGMII using LVDS differential signalling
> > >> > >requires 76 pins, which is the same pincost as the
> > >> > >312.5 MHz XGMII using single-ended drivers.
> > >> > >
> > >> > >In addition, you would need to run at least part of
> > >> > >your logic at the 625 MHz which is significantly
> > >> > >more difficult to implement than staying with a
> > >> > >clock frequency of 312.5 MHz.
> > >> > >
> >
> > >> --
> > >> D. C. Sessions
> > >> dc.sessions@xxxxxxxx
> >
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