RE: SONET/Ethernet clock tolerance
Dave,
Thank you for your understanding. I will appreciate your effort.
Please be sure that the gate count itself would be one of the
columns of the comparison list between your WAN-PHY with
SONET-framing and our XGENIE approach. I think we had better
cover broad raange of interests as wide as possible, such as
gate count
buffer memory, delay
easy implementability, flexibility
WAN compatibility
LAN compatibility
and so on.
These information would be quite helpful for the community to make
the consensus. I know that some of the above columns would be hard
to be quantitative, so please be not too quantitative in your gate
count; I just want to know the order of how lighter it would be.
I will show you a preliminary gate count estimation for our XGENIE
approach, at least until the next Ottawa Meeting. My colleague
Kenji Kawai of NTT and I will work hard to complete it in this April.
Thanks again,
Osamu
At 0:31 PM -0500 00.4.13, David Martin wrote:
http://grouper.ieee.org/groups/802/3/10G_study/email/msg02303.html
> Osamu,
>
> Thanks for clarifying what you're after. We'll provide a gate count estimate for:
>
> 1. Our WAN-compatible PHY proposal
> 2. A fully SONET-compliant OC-192c Section/Line/Path function (1 path)
> 3. A fully SONET-compliant OC-192 Section/Line/Path function (192 paths)
>
> where a gate is defined as a 2-input NAND and the internal processing pipeline
> is 32-bits at 311M. If you could please generate a gate count estimate for your
> XGENIE proposal then we'll have some numbers to compare. Thanks.
>
> ...Dave
-----Original Message-----
From: Osamu ISHIDA [SMTP:ishida@xxxxxxxxxxxxxxxxxxx]
http://grouper.ieee.org/groups/802/3/10G_study/email/msg02289.html