Re: ONLY one ref multiplier?: PMA clock reference
Justin,
I'm aware that the clock is 622.08 MHz for SONET currently and that the jitter
specs are much tighter that required for LAN or WAN PHY operation.
The dilemna we're in, as I see it, is:
- WAN PHY jitter specs seem to be headed in a direction to equal to or close to
SONET whereas LAN PHY jitter specs need only be scaled up from Gigabit Ethernet;
- In order to meet the assumed tighter serial WAN PHY jitter specs, a full rate
XBI reference clock is desirable;
- In order to reduce costs for the serial LAN PHY, a 1/4 or 1/8th speed XBI
reference clock is likely to be adequate. 80.56 MHz crystal oscillators should
be very cheap.
In light of the disparity above, I'd opt for specifying the XBI interface
defining only data and clock signals going in the direction of the data. The
standard would not specify associated clock signals going in the reverse
direction nor reference clocks. See the presentation, "Optional Physical
Instantiation of a PMA Service Interface for Serial PMD’s", by Mr. Stuart
Robinson, et. al.,
http://grouper.ieee.org/groups/802/3/ae/public/may00/robinson_1_0500.pdf, slide
5. The only standardized signals would be TXDATA/TXCLK, RXDATA/CLK. This would
be similar to the documentation of the optional XGMII.
--
Best Regards,
Rich
Jscquake@xxxxxxx wrote:
>
> Hello Rich,
>
> Your proposal sounds good, i.e. to have only a single clock multiple
> (1/4 division) for the reference clock, but I am not sure if this is wise.
> Using a lower rate frequency clock autmatically implies worse jitter
> performance for the PLL's. This is not as much of an issue for the WDM
> case as it is for serial but every psec (or even sub-ps) counts for the
> serial versions. So I would opt to be NOT too restrictive in saying only
> 155-156Mhz xtal osc are allowed. Note that the present community of OC192
> people use the higher clock rate for the reference. Are there any that
> uses the 155MHz as a reference for OC192? Having said all this ... are
> there readily available 644.53125MHz xtal osc.?
>
> Justin
>
> In a message dated 6/16/00 1:03:26 AM Pacific Daylight Time,
> rtaborek@xxxxxxxxxxxxx writes:
>
> > Henning,
> >
> > Sorry about the confusion. I did mention in my note that there would have
> to
> > be
> > two optional clock references specified in the XBI, one for the LAN PHY
> and
> > the
> > other for the WAN PHY.
> >
> > What I should have said is that only one clock MULTIPLE be specified. For
> > example, 161.1328125 MHz is 1/4 of 644.53125 MHz and 155.52 MHz is 1/4 of
> > 622.08
> > MHz. One fourth is a good multiple to use. This means that other multiples
> > should not be required anywhere in the standard, even optionally (i.e.
> 1/8,
> > 1/2,
> > 1/16, 1/1, etc.)
> >
> > Best Regards,
> > Rich
> >
> > --
> >
> > "Lysdal, Henning" wrote:
> > >
> > > Rich,
> > >
> > > I don't see how you can avoid having separate reference clocks for LAN
> and
> > > WAN (with realistic PLL design).
> > >
> > > In the LAN case there are several options
> > > 156.25 MHz (seems to be prefered among serial folks)
> > > 161.1328125 MHz
> > > 644.53125 MHz
> > >
> > > In the WAN case the OIF specifies 622.08 MHz. I know of a lot of people
> > who
> > > also like 155.52 MHz
> > >
> > > Now the problem is: how do you synthesize 9.95328 GHz and 10.3125 GHz
> from
> > > the same reference. If you use a 10 kHz reference, it's easy, but you
> will
> > > most likely have problems with transmit jitter.
> > >
> > > So I haven't been discussing the WAN case at all, since I was under the
> > > impression that WAN PHYs will use existing SONET SerDes using 622.08 MHz
> > > refck.
> > >
> > > Regards,
> > >
> > > Henning
> > >
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