RE: ONLY one ref multiplier?: PMA clock reference
Just as a counter point, we probably address a different market segment, but
all (but one) of our customers have chosen a 622 reference clock, instead of
the 155 option...
David Huff
Executive Director, Marketing
Multilink Technology Corporation
300 Atrium Drive, Second Floor
Somerset, NJ 08873
ph: 732.537.3731
fx: 732.805.9177
www.mltc.com
> -----Original Message-----
> From: owner-stds-802-3-hssg@xxxxxxxx
> [mailto:owner-stds-802-3-hssg@xxxxxxxx]On Behalf Of Lysdal, Henning
> Sent: Monday, June 26, 2000 3:59 AM
> To: stds-802-3-hssg@xxxxxxxx
> Subject: RE: ONLY one ref multiplier?: PMA clock reference
>
>
>
>
> Stuart, Justin, all
>
> I appologize if my answer to the fairly simple question by Justin:
> "Are there any that uses the 155MHz as a reference for OC192?"
> has confused some.
>
> My point was to show technical feasibility, so I'll give it a second try,
> and see if we can get the discussion back on track:
>
> Given the choice between a 155.52MHz reference clock and a 622.08 MHz
> reference clock most of the transceiver vendors (SerDes
> customers), I know,
> CHOOSE 155.52MHz.
>
> It might be easier to get good jitter performance with 622.08MHz
> (644.53MHz), but it is also more expensive.
>
> Maybe we should start discussing which parts of the OIF spec. should be
> copied for Ethernet rather than going over the details of which
> frequencies
> goes where. I guess we can all agree, we need RXDATA, RX_CLK, TX_DATA and
> TX_CLK. What else do we need to specify?
>
> Regards,
>
> Henning
>
> -----Original Message-----
> From: Stuart Brorson [mailto:sdb@xxxxxxxxxxxx]
> Sent: 23. juni 2000 21:56
> To: stds-802-3-hssg@xxxxxxxx
> Subject: RE: ONLY one ref multiplier?: PMA clock reference
>
>
>
> I did not intend to "beat anybody silly". Rather, I wanted to point out
> that designing 10 Gig circuits with very low jitter is *hard*, and the
> difficulty is compounded by using lower speed reference clocks. My friend
> from (unnamed Danish company) unwittingly proved my point by
> announcing that
> their 10 Gig SONET mux chip used a 155 MHz reference. Unfortunately for
> him, that chip is known in the industry for having jitter problems.
>
> More importantly, my real point was that the chip vendors (and
> the standards
> body by extension) should not restrict the designer to using a lower speed
> (i.e. 155 MHz) clock. IMHO, designers want to choose either 155
> or 622, and
> that's the choice the 10 Gig SERDES chip designers correctly give them.
>
> In any event, I discovered after posting my initial message that the
> question of one vs. two clocks involved not the question of 155
> vs. 622, but
> rather how to synthesize both 9.95328 GHz and 10.3125 GHz (WAN vs. LAN)
> with only one reference clock. Read before you post, I always say!
>
> Just to put my two cents into this latter discussion: Since LAN
> line cards
> and WAN line cards often use different optics -- and are
> therefore different
> designs -- I see no reason that one needs to generate 9.95328 GHz and
> 10.3125 GHz off the same crystal. Different boards can have
> different BOMs
> and call out for different oscillators.
>
> Stuart Brorson
> Axiowave Networks
> 100 Nickerson Road
> Marlborough, MA 01752
>
>
> -----Original Message-----
> From: Jonathan Thatcher [mailto:Jonathan.Thatcher@xxxxxxxxxxxxxxxxxxxx]
> Sent: Friday, June 23, 2000 3:30 PM
> To: stds-802-3-hssg@xxxxxxxx
> Cc: Geoffrey O. Thompson (E-mail); David Law (E-mail); Robert M. Grow
> (E-mail); Steven Haddock (E-mail); 'henning.lysdal@xxxxxxxxx'; 'Stuart
> Brorson'; Fred Weniger (E-mail); Joel Goergen (E-mail)
> Subject: RE: ONLY one ref multiplier?: PMA clock reference
> Importance: High
>
>
> Warning!
>
> Excuse me, but me thinks that you (plural) have broken the "respectful and
> dignified" rule here.
>
> Apologizing in advance, frankly, doesn't carry much weight. Try this
> metaphor: "Sorry sir. But, I am going to beat you silly and take your
> wallet." Isn't a courteous mugger kind of an oxymoron? Perhaps this is the
> foundation of an insanity plea? I mean, you can't exactly plead ignorance,
> can you?
>
> Oh, and jumping on the guy while he is down sounds to me more like a
> "Central Park" incident than a technical discussion.
>
> Finally, running down the street screaming with your wallet in the air and
> cash falling out isn't especially wise either.
>
> It would best if everyone avoid the use of company names in all IEEE
> P802.3ae communications. Period.
>
> jonathan
>
> >-----Original Message-----
> >From: Joel Goergen [mailto:joel@xxxxxxxxxxxxxxxxxxx]
> >Sent: Tuesday, June 20, 2000 2:15 PM
> >To: stds-802-3-hssg@xxxxxxxx
> >Subject: Re: ONLY one ref multiplier?: PMA clock reference
> >
> >
> >
> >
> >As a guy who work with Stuart and others on these issues ...I
> >double the "Right
> >On, Brother!"
> >-joel
> >-------------
> >Fred Weniger wrote:
> >
> >> Stuart,
> >>
> >> As a SerDes vendor, I can only say "Right On, Brother!"
> >>
> >> At 08:57 AM 6/20/00 -0400, Stuart Brorson wrote:
> >>
> >> >Please allow me to make a quick comment about 155 vs. 622
> >MHz clocks here.
> >> >I was involved in OC-192 IO card design at my former
> >employer, Nexabit
> >> >Networks (now Lucent Technologies), and have had some
> >experience in this
> >> >department.
> >> >
> >> >It is not my desire to disparage the fine products of Giga
> >here, so please
> >> >accept my apologies in advance. However, the 10 Gig SERDES
> >products from
> >> >Giga (i.e. GD16555 and GD16554) had jitter gen problems, even on the
> >> >company-supplied test board. Amongst other problems,
> >Giga's test board
> >> >incorporated a 155 MHz clock. Designing a low jitter
> >PLL/SERDES chain is
> >> >not very easy.
> >> >
> >> >It is noteworthy that the OIF has speced a 622 MHz
> >reference clock freq for
> >> >the 10 Gig framer/SERDES. That means that clueful PLL
> >vendors have every
> >> >reason to design low-jitter 622 MHz clock modules which can
> >be used -- or
> >> >modified for use -- with 10GigE also.
> >> >
> >> >In any event, most vendors with whom I am aware --
> >including Giga -- allow
> >> >the user to select either a 155 or a 622 MHz reference
> >clock. This allows
> >> >the board designer freedom to choose the design problem he
> >wants to tackle:
> >> >either a lower speed 155 MHz PLL with stringent jitter
> >specs (and a very low
> >> >jitter SERDES), or a higher speed 622 MHz PLL with all the
> >intricacies of RF
> >> >design, but perhaps with an easier jitter (i.e. board
> >noise) problem.
> >> >
> >> >Why not allow two clock frequencies and leave the board
> >designer the freedom
> >> >of choice?
> >> >
> >> >
> >> >Stuart Brorson
> >> >Axiowave Networks
> >> >Marlborough, MA 01752
> >> >
> >> >
> >> >-----Original Message-----
> >> >From: Lysdal, Henning [mailto:henning.lysdal@xxxxxxxxx]
> >> >Sent: Tuesday, June 20, 2000 5:17 AM
> >> >To: 'Jscquake@xxxxxxx'; rtaborek@xxxxxxxxxxx;
> >stds-802-3-hssg@xxxxxxxx
> >> >Subject: RE: ONLY one ref multiplier?: PMA clock reference
> >> >
> >> >
> >> >
> >> >Justin,
> >> >
> >> >In answer to your question:
> >> >
> >> >My company (formerly Giga) has been shipping OC-192 SerDes
> >since 1997 and
> >> >the majority of our customers use 155.52 MHz reference clock.
> >> >
> >> >Regards,
> >> >
> >> >Henning
> >> >
> >> >
> >> >-----Original Message-----
> >> >From: Jscquake@xxxxxxx [mailto:Jscquake@xxxxxxx]
> >> >Sent: 20. juni 2000 00:18
> >> >To: rtaborek@xxxxxxxxxxx; stds-802-3-hssg@xxxxxxxx
> >> >Subject: ONLY one ref multiplier?: PMA clock reference
> >> >
> >> >
> >> >
> >> >
> >> >Hello Rich,
> >> >
> >> >Your proposal sounds good,i.e. to have only a single clock multiple
> >> >(1/4 division) for the reference clock, but I am not sure
> >if this is wise.
> >> >Using
> >> >a lower rate frequency clock autmatically implies worse
> >jitter performance
> >> >for
> >> >the PLL's. This is not as much of an issue for the WDM case
> >as it is for
> >> >serial
> >> >but every psec (or even sub-ps) counts for the serial
> >versions. So I would
> >> >opt
> >> >to be NOT too restrictive in saying only 155-156Mhz xtal
> >osc are allowed.
> >> >Note that the present community of OC192 people use the
> >higher clock rate
> >> >for the reference. Are there any that uses the 155MHz as a
> >reference for
> >> >OC192? Having said all this ... are there readily available
> >> >644.53125MHz xtal osc.?
> >> >
> >> >Justin
> >> >
> >> >In a message dated 6/16/00 1:03:26 AM Pacific Daylight Time,
> >> >rtaborek@xxxxxxxxxxxxx writes:
> >> >
> >> > > Henning,
> >> > >
> >> > > Sorry about the confusion. I did mention in my note
> >that there would have
> >> >
> >> >to
> >> > > be
> >> > > two optional clock references specified in the XBI, one
> >for the LAN PHY
> >> >and
> >> > > the
> >> > > other for the WAN PHY.
> >> > >
> >> > > What I should have said is that only one clock MULTIPLE
> >be specified. For
> >> > > example, 161.1328125 MHz is 1/4 of 644.53125 MHz and
> >155.52 MHz is 1/4 of
> >> >
> >> > > 622.08
> >> > > MHz. One fourth is a good multiple to use. This means that other
> >> >multiples
> >> > > should not be required anywhere in the standard, even
> >optionally (i.e.
> >> >1/8,
> >> > > 1/2,
> >> > > 1/16, 1/1, etc.)
> >> > >
> >> > > Best Regards,
> >> > > Rich
> >> > >
> >> > > --
> >> > >
> >> > > "Lysdal, Henning" wrote:
> >> > > >
> >> > > > Rich,
> >> > > >
> >> > > > I don't see how you can avoid having separate
> >reference clocks for LAN
> >> >and
> >> > > > WAN (with realistic PLL design).
> >> > > >
> >> > > > In the LAN case there are several options
> >> > > > 156.25 MHz (seems to be prefered among serial folks)
> >> > > > 161.1328125 MHz
> >> > > > 644.53125 MHz
> >> > > >
> >> > > > In the WAN case the OIF specifies 622.08 MHz. I know
> >of a lot of people
> >> >
> >> > > who
> >> > > > also like 155.52 MHz
> >> > > >
> >> > > > Now the problem is: how do you synthesize 9.95328 GHz
> >and 10.3125 GHz
> >> >from
> >> > > > the same reference. If you use a 10 kHz reference,
> >it's easy, but you
> >> >will
> >> > > > most likely have problems with transmit jitter.
> >> > > >
> >> > > > So I haven't been discussing the WAN case at all,
> >since I was under the
> >> > > > impression that WAN PHYs will use existing SONET
> >SerDes using 622.08
> >> >MHz
> >> > > > refck.
> >> > > >
> >> > > > Regards,
> >> > > >
> >> > > > Henning
> >> > > >
> >>
> >> Fred Weniger
> >> Gigabit Product Marketing Manager
> >> 805-388-7571
> >> fax: 805-384-5065
> >> weniger@xxxxxxxxxxx
> >> VITESSE
> >> SEMICONDUCTOR CORPORATION
> >
> >--
> >Joel Goergen
> >Force10 Networks
> >1440 McCarthy blvd
> >Milpitas, Ca, 95035
> >
> >Email: joel@xxxxxxxxxxxxxxxxxxx
> >Direct: (408) 571-3694
> >Cell: (612) 670-5930
> >Fax: (408) 571-3550
> >
> >