Re: 64B66B bit ordering
Rick,
>
>Let me try again. I'm referring to the order of the words
>received from the XGMII.
>
>Let's call the 32-bit word transferred on clock tick N,
>WORD[N] and the word transferred on clock tick N+1,
>WORD[N+1]. In your picture on the slide titled "Bit ordering
>sequence", I would say that WORD[N] would wind up in
>BYTE3 thru BYTE0 and I would say that WORD[N+1] would wind
>up in BYTE7 thru BYTE4. Do you agree?
>
>In your "State machine notation conventions" slide, your
>definition of tx_tobe_coded states: "the most recently
>received TXD word in the 35:0 bit locations". To me, the
>"most recently received TXD" would correspond to WORD[N+1]
>in my definition above.
>
>I guess what I'm missing is a bit to byte map. I picture
>bits [35:0] corresponding to BYTE3 thru BYTE0 but these
>should hold WORD[N].
>
>Thanks,
>Ben
Ben,
Hopefully the following will clarify the picture.
Consider the XGMII data flow:
(pg 8: http://grouper.ieee.org/groups/802/3/10G_study/public/nov99/frazier_1_1199.pdf)
lane# / time -> N N+1
-------------------------
0 D0 D4
1 D1 D5
2 D2 D6
3 D3 D7
We have two ways of describing what to do next (ignoring control
flag processing)
Description method 1
------------------------
Assemble into a 64 bit register
_______________________________________________________
| |..| | |..| | |..| | |..| | |..| | |..| | |..| | |..| |
-------------------------------------------------------
7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0
D7 D6 D5 D4 D3 D2 D1 D0
Add the two bit prefix
65 .................. 0
___________________________________________________________
| |..| | |..| | |..| | |..| | |..| | |..| | |..| | |..| |1|0|
------------------------------------------------------------
7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0
D7 D6 D5 D4 D3 D2 D1 D0
Now serially shift from bit 0 through bit 65.
Advantage: The 66bit register holds the data in the order it will
be shifted.
Disadvantage: The data is shifted from right to left, while a human
would read octets from left to right.
Description method 2 (pg 7:http://grouper.ieee.org/groups/802/3/ae/public/may00/walker_1_0500.pdf)
--------------------
Assemble into a 64 bit register
_______________________________________________________
| |..| | |..| | |..| | |..| | |..| | |..| | |..| | |..| |
-------------------------------------------------------
7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0
D0 D1 D2 D3 D4 D5 D6 D7
Add the two bit prefix
65 .................... 0
____________________________________________________________
|0|1| |..| | |..| | |..| | |..| | |..| | |..| | |..| | |..| |
------------------------------------------------------------
7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0
D0 D1 D2 D3 D4 D5 D6 D7
Now serially shift bit 65, 64. and the octets from the left
to right. But within each octet, shift from 0 .. 7.
Advantage: Octet shifting matches with our tendency to read from
left to right.
Disdvantage: Describing the shifting becomes a bit more complicated.
User feedback will help identify the most convenient representation.
Regards,
Birdy