RE: FW: XGMII Clocks
See below.
>-----Original Message-----
>From: Rich Taborek [mailto:rtaborek@xxxxxxxxxxxxx]
>Sent: Saturday, September 09, 2000 3:17 PM
>To: HSSG
>Subject: Re: FW: XGMII Clocks
>
>
>
>Curt,
>
>I agree with you that the "best bang for the buck" insofar as XGMII
>interface operations goes may be to lower voltage swings and better
>match impedance.
>
>The alternative, but perhaps more complex approach, would be to retain
>the current source centered clocking and have the XGMII receiver adjust
>perform precise phase positioning in an implementation. This alternative
>is implementation dependent regardless of the clock I/O signal
>definition.
156 DDR, is not that hard that it warrents receiver adjustements or training
sequences.
Source centered clock, will have less SSO on the clock then if clock
and data switch simultaneously. However not so much improvment
that it really matters. Careful clock design can yield almost same results.
If you need to shift clock at rcv, board traces are great "delay lines" !!
>In any case, two-phase or differential clocks DDR clocking schemes do
>not seem to help. In addition, they both cost pins.
It would be benefitial to have all drivers same type. The benefits for
a short bus (6-12) of haveing differential clocks is not worth it.
Prudent care of clocks should be enough.
If we switch to a lower swing I/O like HSTL, I would also like to
see the option to either terminate at the source or the end.
Some companies have build impedance match driver which would work
great for this application. Since the source no only drives a
half step, EMI, SSO, gets cut in half again !!
However for companies that doe not have this technology, end termination
is a must options.
-Curt Berg-
Extreme Networks,
>Best Regards,
>Rich
--
Curt Berg wrote:
>
> Hi,
> With two phase clocks you trade duty cycle problem against
> managing two clocks and two paths. You still need to accurately
> put the second clocks posedge in the middle, and you have the same
> "duty cycle" distrotion on data. Not easy to put the 2nd pos edge
> in the middle if you don't start with a 2x clock. Well if you have
> a 2x clock then it is easy to generate a symmetric clock !
>
> The max gitter between clock and data is what kills you.
> It is not enought to run best case and worst case sims, instead
> weak p strong n, and strong p weak n, will make your make your
> live difficult. Basically standard ASIC STA is not useful to analys
> this problem ! Most bang for the buck is a lower voltage swing,
> and more matched impedance. All high speed SRAMs, with DDR (that I know
> of) have gone to HSTL, with impedance controlled drivers for very good
> reasons !!
>
> -Curt Berg-
> Extreme Networks
-------------------------------------------------------
Richard Taborek Sr. Phone: 408-845-6102
Chief Technology Officer Cell: 408-832-3957
nSerial Corporation Fax: 408-845-6114
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