RE: Clause 51 (XSBI) questions

["Erik Trounce" <erikt@xxxxxxxxxxxxxxxxxx>]

Henning,

Thanks for the clarifications.  I have one comment on your
last answer:

In message "Clause 51 (XSBI) questions", Lysdal, Henning writes:
>4. Is there a reason the edges are reversed between OIF SFI-4
>and the draft 1.0?  Specifically, SFI-4 specifies the Rx data
>valid around the RX_CLK positive edge while the draft
>specifies Rx data valid around the RX_CLK falling edge.  I
>realize you can simply switch your differential inputs to
>achieve the switch.
><<<<<<<<<<<<<< ANSWER >>>>>>>>>>>>
>The interface timing is specified as an input timing requirement using
setup
>and hold times. Positioning the falling edge of the clock in the center
of
>the databit implies that data is latched out of the PMA device on the
rising
>edge. The OIF framer input and SerDes output spec requires system
>implementors to invert the recieve clock on the board. For clarity we
have
>chosen to change the sign in the actual specification, so no
>clock-inversions are required by system implementors.

If I, as a PCS device designer, chose to implement the XSBI receive
path such that receive data was clocked in on the RX_CLK rising
edge, would there be any ramifications other than the board designer
having to reverse the connections between the _N and _P pins of
the RX_CLK input?  The OIF has specified that the SERDES (PMA)
will send data out on the RX_CLK rising edge, and that the SONET
Framer (PCS) will clock data in on the RX_CLK rising edge.  This
implies an inversion of the RX_CLK clock on the board.  I don't
see any reason why the XSBI could not follow the same protocol,
keeping everything positive edge triggered.

Cheers,
Erik Trounce