Re: 64b/66b scrambler
Eric,
Sorry for misunderstanding your last question. I'll
try harder on these.
Eric Ng wrote:
>
> Hi,
>
> I have some questions on the 64b/66b scrambler.
> In sec 49.2.6 of draft D1.0 stated that there is no
> reqiurement on the initial value. Please correct me
> if I'm wrong. The descrambler can recover 58th bit
> by doing S0^S39^S58 and so do the subsequent bits.
>
> (1)
> What happen at power up or the system is reset? Are we
> assuming that the first few frames will be used for
> synchronization? That we will be well over the first
> 58bits by the time, the first valid payload is recevied.
Yes, since it takes at least 64 frames to become in sync,
as long as your scrambler is operating while your sync
machine is running, everything should be stable once you
become in sync.
>
> (2)
> Also, once the scrambler/descarmbler are initialized at
> power up or system reset, the shift register will not
> reset at packet boundary and/or SPE boundary.
This is correct. As Pat pointed out, if bit errors occur
the descrambler will generate bad data, based on the taps,
until the errors are flushed out of the descrambler but
they will eventually clear.
>
> (3)
> In the bluebook, the sample test vector, the scrambler
> is initialized to all 1's. Is this the default value
> at power up reset?
To recreate the exact test pattern, yes this is the case.
In real life, because it is not necessary that one
implementation reset its PCS scrambler to the same value
as another implementation, it is true that bit streams
from 2, otherwise identical designs and packet streams,
will be different. Because the receiver will descramble
based on the input stream, it won't matter to the
descrambler.
I can't wait to hear where I screwed these answers up :)
Ben
>
> Thanks in advance.
>
> cheers,
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