Re: Clause 51 (XSBI) question
Hello Rich,
I need to fix up the nomenclature. The <0,1> was meant so show that
there were differential lines for the clocks, the data, etc...
It is not intended to distinguish upper and lower bytes clocking. I believe
this
was a method used in Fibre Channel ICs. For the XSBI, all data (lower or
upper byte)
is synchronized to one edge. The diagrams show no "<0,1>". For the next
edit, a high for a clock diagram means the <1> line is high and the <0> is
low.
Hope this helps. Regards.
Justin Chang
Quake Technologies, Inc.
50 Airport Parkway, San Jose, CA. 95110
Tel: 408-437-7723 email: justin@xxxxxxxxxxxxx
Fax: 408-437-4923 internet: www.quaketech.com
In a message dated 10/13/00 5:01:26 PM Pacific Daylight Time,
rick.rabinovich@xxxxxxxxxxxxxx writes:
> need some clarification to the obvious. I see in clause 51 references to
> PMA_TX_CLK<0,1>, PMA_TXCLK_SRC<0,1>, and PMA_RX_CLK<0,1>. Is it correct to
> assume that <0> refers to (tx/rx)_data_group<7:0> and <1> refers to
> (tx/rx)_data_group<15:8>, in other words each byte has its own
synchronizing
> clock? If that is the case, do we need two separate clocks on each
> direction?
> Thank you,
>
> Rick Rabinovich
>
> Rick Rabinovich
> Hardware Group Lead Engineer
> System Architect
> Spirent Communications
> 26750 Agoura Road
> Calabasas, CA 91302
> Phone: 818-676-2476
> Fax : 818-880-9293