Re: I/F locations
Ted,
I agree that this is an implementation question, so I'll restrict my
comments to baseline P802.3ae technologies and implementations based on
those technologies.
The primary difference between the XSBI and XAUI is that the former is a
parallel bus and the latter is a serial bus. I'd like to start of this
note with a historical perspective of parallel vs. serial interfaces
employed between a transceiver module and the MAC.
End user flexibility and economies of scale have been proven by Ethernet
LAN equipment including Gigabit Ethernet. Virtually all the backbone
Gigabit Ethernet equipment currently employ low cost pluggable or fixed
optical modules. These optical modules attach to a SerDes (an then to
PHY/MAC) with a low pin count, 1.25 Gbps, Serial, 8b/10b encoded
interface. I am pointing this out because, for most datacom
applications, serial interfaces are already considered to be the defacto
and most cost effective way to connect the an optical module to the
MAC/PHY. This is also rapidly becoming true for most telecom
applications through OC-48 (2.488 Gbps). In general, SerDes technology
at ~OC-48 and below can be integrated with the MAC/Framer. The
technology of choice for interfacing a transceiver module to the MAC is
already a single serial lane rather than a parallel interface.
At a data rate of 10 Gbps, a low pin count, 3.125 Gbps, 4-lane Serial,
8b/10b encoded interface is proposed for connecting an optical module to
its SerDes on the system side (see XGP). The same interface is
applicable to all proposed P802.3ae PHYs including 10GBASE-LW4, although
not currently accepted as a baseline proposal. The advantages of a
XAUI-based serial bus over a parallel bus such as the XSBI between a
transceiver module and the MAC at ~10 Gbps include the following:
Low pin count; low power; clockless; low EMI (no clock); internal PLLs
for jitter attenuation and precision clocking; frequency agility
(FEC/non-FEC); scalable in speed; scalable in #lanes; error detection
capability; bit error rate integratable in CMOS at 0.25 um and below;
very low die area/#gates; may be AC or DC coupled; low swing
differential I/O; supports min 20" FR-4 PCB traces; supports simple
transmit equalization for >50% PCB trace increase; fast byte
synchronization; high skew tolerance and multi-bit deskew capability;
high bit transition density; low, constrained run length; optics
friendly; control code space; robust packet delimiting; protocol
independent; PMD independent.
Either the XAUI or XSBI will work for interfacing a transceiver module
to the MAC. At 10 Gbps and in general, older and telecom applications
employ parallel interfaces such as the XSBI and most newer and datacom
applications will/use XAUI. The same general directions will prevail at
data rates of 40 and 100 Gbps.
--
Best Regards,
Rich
"Speers, Ted" wrote:
>
> I realize this is an implementation question, but is there a likely
> demarcation point between the transceiver module and the MAC. It's hard to
> sort out a lot of these discussions (LSS, XAUI/SUPI, etc.) without have this
> in proper context.
>
> Possible points of demarcation would seem to be either the XAUI or
> the XSBI interfaces. I've seen presentations suggesting both.
>
> It seems that a break at the XSBI would offer the most in terms of
> end-user flexibility and economies of scale for both the users and the
> vendors ... with one exception, 10GBASE-X4 would be left out in the cold
> because, as far as I can tell, there is no way to implement the standard
> across an XSBI.
>
> Ted Speers
> Strategic Marketing
> Actel
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