Re: Clause 45 (D2.0) Questions

["Edward Turner" <Edward_Turner@xxxxxxxxxxxx>]

Boaz,

1/ The duplication is unnecessary and I have raised comments for the removal of
the 'XAUI link status' bit for both the PHY-XGXS and DTE-XGXS (removal of bits
5.24.12 and 4.24.12).

2/ 'Transmit signal clock to output delay' (item ST1) and items ST2 and ST3 in
45.4.5.8 are copy and paste artifacts from Clause 22. They should not be there
and I will raise a comment for their removal from the table.

Regards
Ed





Boaz Shahar <boazs@xxxxxxxxxxxx> on 13/12/2000 14:02:13

Sent by:  Boaz Shahar <boazs@xxxxxxxxxxxx>


To:   "HSSG
cc:    (Edward Turner/GB/3Com)
Subject:  Clause 45 (D2.0) Questions





Hello There,

1)The status bit "XAUI Transmit link status" in the PHY-XGXS status register
(table 45-29) seems to be duplicated in the "Lane Status Register". The same
duplication occurs in the DTE-XGXS register description as well.  Why this
is needed?

2)The term "Transmit signal clock to output delay" (Section 45.4.5.8) refers
to the delay between the MDC edge to the MDIO data? If so, what is reffered
by the term "MDIO clock to output delay"?

Thanks,
Boaz