RE: delay constraints from XGMII to XAUI
As a system implementer, how do I improve the probability of buying parts
from different vendors to build my system with confidence that the total
delay will have been allocated by each vendor independently and that my
system will still meet the total delay requirement?
If you feel strongly about this though, you should submit a ballot comment.
--Bob
-----Original Message-----
From: Boaz Shahar [mailto:boazs@xxxxxxxxxxxx]
Sent: Thursday, December 14, 2000 12:43 AM
To: HSSG
Subject: RE: delay constraints from XGMII to XAUI
Hi,
I think that the standard should constraint only the total delay from the
MDI to the XGMII, and leave internal partitioning to implementation.
Boaz
> -----Original Message-----
> From: Rich Taborek [mailto:rtaborek@xxxxxxxxxxxxx]
> Sent: Thursday, December 14, 2000 12:18 AM
> To: HSSG
> Subject: Re: delay constraints from XGMII to XAUI
>
>
>
> Bob,
>
> Agreed.
>
> Steven,
>
> Just to carify, the MDI to XGMII delay includes the XAUI to
> XGMII delay.
>
> Best Regards,
> Rich
>
> --
>
> "Grow, Bob" wrote:
> >
> > The only MAC requirement I can think of for bounding the
> lower layer delay
> > is for buffer sizing for 802.3x flow control. That has
> been the factor for
> > keeping the delay tables in various clauses.
> >
> > --Bob Grow
> >
> > -----Original Message-----
> > From: Steven Shen [mailto:ss_shen@xxxxxxxxxxxxxxxxx]
> > Sent: Wednesday, December 13, 2000 11:58 AM
> > To: stds-802-3-hssg@xxxxxxxx
> > Subject: delay constraints from XGMII to XAUI
> >
> > Hi all:
> >
> > In D2.0 table 48.5 defines the MDI to XGMII delay
> constraints to be 272
> > UI. I wonder that "is there any delay constraints on XAUI to XGMII
> > (PCS+PMA)"?
> >
> > thanks
> >
> > best regards
> >
> > Steven Shen
> > Silicon Bridge Inc.
>
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