Re: PCS FIFO Empty condition
Anupama,
Since this is design specific, for a small consulting fee
(5 or 6 figures :-), I could help you fix it.
Your clock tolerance fifo must be designed to accommodate
the worst case clock variation (+/- 100 ppm or perhaps
more if you want to be very robust), the largest packet
size (1522 bytes or perhaps more if your customers desire
jumbo frames) and the possibility that you may have to
wait multiple packets to find an IPG that is large enough
to remove a column from (you must keep at least 5 octets
of IPG between packets and multiple hops could exist, all
wanting to remove IPG at the same time - e.g. XAUI on both
ends of the link).
If you've done your math properly and designed it
correctly, it shouldn't go empty (or full) during a packet.
There should be time during the IPGs to remove or add fill
so you don't have packet corruption. After all this, if
your fifo still goes empty or full during a packet, the
packet must be considered in error. If you insert a column
of IDLE then you're relying on a missing /T/ to corrupt
the packet then a missing /S/ and bad preamble to corrupt
the rest of what you're putting through. If you insert a
column of /E/, the packet won't be split in half at the
RS but will still result in an error at the MAC.
Good luck. Since this is design specific, let's pull any
more discussion of this off the reflector and make sure
you get that consulting PO signed :)
Ben
> Anupama Agashe wrote:
>
> Hi Ben,
>
> Thanks a lot for ur reply.
>
> I was talking about the FIFO used for clk tolerances.
> I just repeat the conclusion, PHY should not let fifo go empty in
> between the packet data, maintaining pkt-integrity (by adjusting the
> IPG). My quenstion was design specfic. If due to some mechanism
> problems, suppose, the fifo goes empty, then the idle data should be
> sent on the line. No error coulmn should be inserted.
>
> regards,
> Anupama
>
> -----Original Message-----
> From: Ben Brown [mailto:bbrown@xxxxxxxx]
> Sent: Friday, January 05, 2001 9:17 PM
> To: 802.3ae
> Subject: Re: PCS FIFO Empty condition
>
> Anupama,
>
> I'm going to suggest that your FIFO is an implementation
> specific entity. There is nothing in the standard that
> requires the use of a FIFO in the PCS.
>
> If there is no incoming data stream, it is expected that
> local fault will be generated towards the RS.
>
> If you are referring to clock tolerance adjustments, an
> extra column of IDLEs are inserted during the IPG.
>
> Regards,
> Ben
>
> > Anupama Agashe wrote:
> >
> > Hi,
> >
> > What action should be taken by the transmit PCS FIFO, when it goes
> > EMPTY (may be in between a packet-data, or IPG) due to some
> > conditions?
> >
> > My understanding is that it should continuously insert idles till
> > normal condition is restored. But is it also necessary to
> specifically
> > insert atleast one ERROR column under this condition? The receive
> MAC
> > on the other side is going to discard the respective packet under
> both
> > the conditions (since packet gets broken). So, does the PHY need to
> > indicate empty through the error indication?
> >
> > regards,
> > Anupama
>
> --
> -----------------------------------------
> Benjamin Brown
> AMCC
> 2 Commerce Park West
> Suite 104
> Bedford NH 03110
> 603-641-9837 - Work
> 603-491-0296 - Cell
> 603-626-7455 - Fax
> 603-798-4115 - Home Office
> bbrown@xxxxxxxx
> -----------------------------------------
--
-----------------------------------------
Benjamin Brown
AMCC
2 Commerce Park West
Suite 104
Bedford NH 03110
603-641-9837 - Work
603-491-0296 - Cell
603-626-7455 - Fax
603-798-4115 - Home Office
bbrown@xxxxxxxx
-----------------------------------------