RE: Clock Tolerance and WAN PHY

["David Martin" <dwmartin@xxxxxxxxxxxxxxxxxx>]

Title: RE: Clock Tolerance and WAN PHY

James, Luigi,

The 'ELTE' is also necessary to fill in the remaining SONET
overhead.

...Dave

David W. Martin
Nortel Networks
+1 613 765-2901
+1 613 765-0769 (fax) 
dwmartin@xxxxxxxxxxxxxxxxxx <mailto:dwmartin@xxxxxxxxxxxxxxxxxx>

=========================

-----Original Message-----
From: James Colin [mailto:james_colin_j@xxxxxxxxx]
Sent: Sunday, January 21, 2001 3:54 AM
To: Luigi.Ronchetti@xxxxxxxxxxxxxxxx; tripathi@xxxxxxxxxxxx
Cc: stds-802-3-hssg@xxxxxxxx
Subject: Clock Tolerance and WAN PHY

Luigi,
I think that the motto in the WAN PHY standard is the
introduction of a new framing scheme (As opposed to
POS), rather than being gluelessly connectable to the
SONET network. The WAN PHY is supposed to be connected
to a SONET LTE (ELTE) that is doing clock drift and
jitter adjustments.

Even if the WAN PHY Clock requirements were identical
to those of SONET, I'm not sure if the ELTE is still
needed or the WAN PHY can be directly interface to the
SONET ring. Can anybody comment on that?

James

--- Luigi.Ronchetti@xxxxxxxxxxxxxxxx wrote:
> Hi Devendra and all,
>
> I think that is not enough to reduce the clock
> tolerance to 50ppm.
>
> As far as I know, ITU-T is going to approve
> (February 2001) a new
> recommendation (G.709) that defines OTN (Optical
> Transport Network).
> Future optical backbones over long distances will
> likely to be realized
> using G.709 and this will happen before 10 GbE final
> approval.
>
> In G.709, among the others, a CBR10G client signal
> is defined as "a
> constant bit rate signal of 9953280 kbit/s +/-20
> ppm" (for example an
> OC-192/STM-64 signal and then, in principle, also a
> 10 GbE WAN signal).
>
> So, in my opinion, at least for a 10 GbE WAN signal,
> the clock
> tolerance should be 20ppm.
>
> Best regards,
> Luigi
>       __
>       \/                        Luigi Ronchetti
> A L C A T E L  via Trento, 30 - 20059 Vimercate (MI)
> Italy
>    TND R&D     phone: +39-039-686.4793 (Alcanet
> 2-210-(3)4793)
>                fax:   +39-039-686.3590 (Alcanet
> 2-210-(3)3590)
>              
> mailto:luigi.ronchetti@xxxxxxxxxxxxxxxx
>
> > -----Original Message-----
> > From: tripathi@xxxxxxxxxxxx
> [mailto:tripathi@xxxxxxxxxxxx]
> > Sent: Tuesday, January 09, 2001 10:50 PM
> > To: stds-802-3-hssg@xxxxxxxx
> > Cc: tripathi@xxxxxxxxxxxx
> > Subject: Clock tolerance
> >
> >
> >
> > Hi,
> >
> > Right now we are specifying the clock tolerance of
> 100 ppm. Currently
> > in-expensive
> > oscillators are available with tolerance value
> less than 50
> > ppm. Just like
> > we are moving
> > voltage levels, it is time we revise the tolerance
> value too.
> > The elastic
> > buffer
> > requirements get simplified by this assumption. I
> propose
> > that we reduce it
> > to 50 ppm.
> >
> > Regards,
> > Devendra Tripathi
> > VidyaWeb, Inc
> >
>

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