RE: XGMII Clock Duty Cycle
Venu,
I think it should not be worse than 40/60. At 30% we are talking about data
capture at 1.92 ns distance which is very tight. At 40% it will become 2.56
ns
which not whole lot but respectable number.
Regards,
Devendra Tripathi
VidyaWeb, Inc
90 Great Oaks Blvd #206
San Jose, Ca 95119
Tel: (408)226-6800,
Direct: (408)363-2375
Fax: (408)226-6862
> -----Original Message-----
> From: owner-stds-802-3-hssg@xxxxxxxx
> [mailto:owner-stds-802-3-hssg@xxxxxxxx]On Behalf Of Vinu Arumugham
> Sent: Tuesday, February 27, 2001 9:21 AM
> To: Boaz Shahar
> Cc: James Colin; stds-802-3-hssg@xxxxxxxx
> Subject: Re: XGMII Clock Duty Cycle
>
>
>
> The current specification will only guarantee that the duty cycle
> will be no
> worse than 30%/70%. If this is insufficient, a separate duty cycle
> specification will be necessary.
>
> Thanks,
> Vinu
>
>
> Boaz Shahar wrote:
>
> > Hi,
> > In implementations working with TXCLK as the digital portion clock, you
> > sample XGMII column in rising edge, then you sample the next
> XGMII column
> > with falling edge, and then sample again a pair of column with
> rising edge
> > for the internal logic. So, in order to enable such implementations, the
> > distance from rising edge to falling edge of the clock is needed.
> > Boaz
> >
> > > -----Original Message-----
> > > From: Vinu Arumugham [mailto:vinu@xxxxxxxxx]
> > > Sent: Monday, February 26, 2001 8:57 PM
> > > To: James Colin
> > > Cc: stds-802-3-hssg@xxxxxxxx
> > > Subject: Re: XGMII Clock Duty Cycle
> > >
> > >
> > >
> > > James,
> > >
> > > The driver tsetup and thold requirements already place a limit on the
> > > duty cycle variation of the DDR clock output.
> > >
> > > I think a separate duty cycle specification will be redundant and may
> > > reduce flexibility in the transmitter output design.
> > >
> > > Do you see a need for a separate duty cycle specification?
> > >
> > > Thanks,
> > > Vinu
> > >
> > >
> > > James Colin wrote:
> > >
> > > > Hi,
> > > > I searched carefully for XGMII Clock duty cycle in
> > > > Clause 46 of D2.1, Nevertheless, I could not find
> > > > anything. Can anyone help with this? What is the duty
> > > > cycle of the XGMII DDR Clock?
> > > > Thanks
> > > > James.
> > > >
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>