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RE: XAUI SJ jitter test

To: "'Rogers, Shawn'" <s-rogers@xxxxxx>, "'Tom Lindsay'" <Tom.Lindsay@xxxxxxxxx>
Subject: RE: XAUI SJ jitter test
From: Boaz Shahar <boazs@xxxxxxxxxxxx>
Date: Tue, 13 Mar 2001 20:22:10 +0200
Cc: HSSG <stds-802-3-hssg@xxxxxxxx>
Sender: owner-stds-802-3-hssg@xxxxxxxx

Shawn,

The BERT is the problem or it is the Pattern Generator/Signal Generator?

Rgards,

Boaz

-----Original Message-----
From: Rogers, Shawn [mailto:s-rogers@xxxxxx]
Sent: Tuesday, March 06, 2001 6:32 PM
To: 'Tom Lindsay'
Cc: HSSG
Subject: XAUI SJ jitter test

Tom, I'm asking you this as I seem to recall from the Jan Interim you presented on the Annex 48A jitter test approach. If I am in error please forgive me.

In D2.1, Clause 47, Page 285, Figure 47-8 shows Sinusoidal Jitter Tolerance Mask that requires 0.1UI SJ tolerance up to 20Mhz. Can you or anyone on the reflector describe how this limit can be tested. I am told that the HP 3G and 12G BERTs can only modulate up to 10Mhz.

Regards,

Shawn Rogers

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