Re: Implementation vs. Standard
Pat,
the MAC statemachines dont say "PCS shall implement its
Transmit process as depicted in Figure 48..., including compliance
with the associated state variables as specified in 48..."
The PCS statemachines do, and have since 100B Ethernet days.
Should this statement be removed?
justin
pat_thaler@xxxxxxxxxxx wrote:
>
> Or in the immortal words of 802.3 (clause 1.2.1 and other places):
>
> The models presented by state diagrams are intended as the primary
> specifications of the functions to be provided. It is important to
> distinguish, however, between a model and a real implementation. The models
> are optimized for simplicity and clarity of presentation, while any
> realistic implementation may place heavier emphasis on efficiency and
> suitability to a particular implementation technology. It is the functional
> behavior of any unit that must match the standard, not its internal
> structure. The internal details of the model are
> useful only to the extent that they specify the external behavior clearly
> and precisely.
>
> I don't know of any implementations that put the MAC state machine in real
> Pascal code.
>
> Regards,
> Pat
>
> -----Original Message-----
> From: Booth, Bradley [mailto:bradley.booth@xxxxxxxxx]
> Sent: Tuesday, March 27, 2001 10:02 AM
> To: 802.3ae
> Subject: RE: Implementation vs. Standard
>
> Justin,
>
> If the circuit you design complies with the standard, how is anyone to know
> how you implemented it? What matters is what it seen on the MDI. If that
> looks correct, then you can implement it in FORTRAN for all I care.
>
> Cheers,
> Brad
>
> -----Original Message-----
> From: Justin Gaither [mailto:jgaither@xxxxxxxxxxxxxxx]
> Sent: Tuesday, March 27, 2001 10:59 AM
> To: Taborek, Rich; 802.3ae
> Subject: Implementation vs. Standard
>
> << File: Card for Justin Gaither >> Rich,
> a while back I sent a message about PUDI(/INVALID/)
> and decoder
> placement. In your reply you said:
> Rich Taborek wrote:
> >
> > Justin,
> >
> > The Sync state machine is written to operate in the 10B
> domain as is the
> > Deskew state machine.
> >
> > The 10GBASE-X PCS does not mandate the location and number
> of decoders
> > in an implementation. The PCS Sync and Receive state
> machine structure
> > is virtually identical to that of the 1000BASE-X PHY. The
> DECODE
> > function can be located elsewhere, but I don't view such a
> change as
> > being more or less "correct" than it's current location.
> >
> > As to your second point, Invalid represent a superset of
> invalid
> > code-groups and running disparity errors. Therefore,
> running disparity
> > error is not a suitable replacement for Invalid.
> >
> > Best Regards,
> > Rich
>
> I am new to the standards based design, so I dont quite
> understand where
> the line between standard and implementation is drawn.
>
> It was my understanding from the spec. that the "PCS shall
> implement its
> Transmit process as depicted in Figure 48..., including
> compliance with
> the associated state variables as specified in 48..."
> means, I have to
> put the decoder where specified, and not before the deskew
> and sync
> state machines. Now I know I could design a circuit that
> behaves the
> same as the standard but place the decoder before the deskew
> and sync,
> but is this still compliant? Can I still select Yes in the
> PICS to
> meeting the requirements of the State Machines?
>
> Regards,
> justin
>
> --
> Justin Gaither Phone: 512-306-7292
> x529
> RocketChips a Division of Xilinx Fax: 512-306-7293
> 500 N. Capital of TX Hwy.
> Bldg 3 email:
> jgaither@xxxxxxxxxxxxxxx
> Austin, TX 78746 WWW: www.rocketchips.com
--
Justin Gaither Phone: 512-306-7292 x529
RocketChips a Division of Xilinx Fax: 512-306-7293
500 N. Capital of TX Hwy.
Bldg 3 email: jgaither@xxxxxxxxxxxxxxx
Austin, TX 78746 WWW: www.rocketchips.com
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