RE: Management PMA/PMD registers for XAUI
Boaz,
Unless I've missed some change that occurred in D3.0, MDIO is an optional
part of the standard. No sublayer is required to provide an MDIO. There is
some text that recommends or requires access through proprietary means to
some managment bits when an MDIO is not present, but I don't think there is
such text for the PMA lock bit.
Secondly, I don't think that a DTE-XGXS to PMD with nothing in between would
be a valid implementation. The stack with a XAUI interface is:
RS -> DTE-XGXS -> PHY-XGXS -> PCS -> PMA -> PMD.
When the PMD is 10GBASE-X, then the combination of PHY-XGXS and PCS is just
translating a 4 lane 8B/10B signal to an XGMII signal and back into a 4-lane
8B/10B signal. It is obviously possible to remove most of the PHY-XGXS and
PCS logic to just pass through the 8B/10B signal.
BUT XAUI and the fiber media have separate jitter budgets and there isn't
enough slack to combine them. One might get away with that in a very careful
implementation, but not if one is going to use the XAUI as a compatability
interface. (If you want to do an implementation without internal
compatability interfaces and you meet all the specs at the MDIO, you can do
your internal layering any way you want.)
If one is doing a XAUI to 10GBASE-X PMD module, then there will be at least
a retimer in it. The 10GBASE-X PMA is pretty much just the retimer. Rich's
diagram in the presentation you mention doesn't get into that detail, but
the words that are in the draft on the subject do mention the presence of
the retimer.
Pat
-----Original Message-----
From: Boaz Shahar [mailto:boazs@xxxxxxxxxxxx]
Sent: Tuesday, April 10, 2001 12:22 PM
To: 'pat_thaler@xxxxxxxxxxx'; Boaz Shahar; jgaither@xxxxxxxxxxxxxxx;
stds-802-3-hssg@xxxxxxxx
Subject: RE: Management PMA/PMD registers for XAUI
Pat,
I'm also thinking that the XGXS does not need a separate Lock bit, and all
its status contain enough info. The question is if the standard requires it
for compliancy or not.
For example: in a system of DTE-XGXS+PMD (As depicted in Rich Taborek prsnt.
from May 2000, taborek_3_0500 p. 8), where the XGXS implements both 10GB-X
PCS and 10GB-X PMA, the compliancy requirement is to implement the address
spaces of both the PMA/PMD and the 8B/10B PCS, or the register space of the
XGXS is enough for compliancy of the system?
Boaz
> -----Original Message-----
> From: pat_thaler@xxxxxxxxxxx [mailto:pat_thaler@xxxxxxxxxxx]
> Sent: Tuesday, April 10, 2001 9:54 PM
> To: boazs@xxxxxxxxxxxx; pat_thaler@xxxxxxxxxxx;
> jgaither@xxxxxxxxxxxxxxx; stds-802-3-hssg@xxxxxxxx
> Subject: RE: Management PMA/PMD registers for XAUI
>
>
> Boaz,
>
> There aren't any separate PMA registers. They are PMA/PMD
> registers and the
> bits in them that apply to 10GBASE-X largely relate to PMD
> functionality.
> The one bit that is specifically PMA is 1.1.2 receive link
> status which
> tells whether the PMA is locked. XGXS has lane sync bits and
> I don't think
> it needs a separate lock bit.
>
> Pat
>
> -----Original Message-----
> From: Boaz Shahar [mailto:boazs@xxxxxxxxxxxx]
> Sent: Tuesday, April 10, 2001 11:23 AM
> To: 'THALER,PAT (A-Roseville,ex1)'; Justin Gaither; 802.3ae
> Subject: RE: Management PMA/PMD registers for XAUI
>
>
> Pat,
> The XGXS layer implements all the functions that are
> associated with both
> the 10GBASE-X PCS and 10GBASE-X PMA defined in clause 48. If
> in the XGXS
> case there is no need for the implementation of the PMA
> registers (And I
> think that there is NO need for that), why it is needed in the case of
> 10GBASE-X PMA?
> Boaz
>
> > -----Original Message-----
> > From: THALER,PAT (A-Roseville,ex1) [mailto:pat_thaler@xxxxxxxxxxx]
> > Sent: Tuesday, April 10, 2001 7:58 PM
> > To: Justin Gaither; 802.3ae
> > Subject: RE: Management PMA/PMD registers for XAUI
> >
> >
> >
> > Justin,
> >
> > As currently defined, there is only a single PMA in the
> stack which is
> > attached to the PMD. An XGXS doesn't have a separate PMA
> > sublayer. I think
> > we should leave it that way. We already fragment the physical
> > layer into a
> > lot of sublayers.
> >
> > Regards,
> > Pat
> >
> > -----Original Message-----
> > From: Justin Gaither [mailto:jgaither@xxxxxxxxxxxxxxx]
> > Sent: Tuesday, April 10, 2001 7:19 AM
> > To: 802.3ae
> > Subject: Management PMA/PMD registers for XAUI
> >
> >
> >
> > When a 10GBase-X PCS is being used as a PHY XGXS, it has a
> XAUI PMA.
> > Should this PMA have all of the Management registers
> > specified (ie. 1.0,
> > 1.1, 1.2&1.3, 1.4, 1.5, 1.8, 1.9)? Or are these registers for the
> > PMA/PMD that actually tied to the fiber PMD?
> >
> > Regards,
> >
> > justin
> >
> > --
> > Justin Gaither Phone: 512-306-7292 x529
> > RocketChips a Division of Xilinx Fax: 512-306-7293
> > 500 N. Capital of TX Hwy.
> > Bldg 3 email: jgaither@xxxxxxxxxxxxxxx
> > Austin, TX 78746 WWW: www.rocketchips.com
> >
>