Re: XGMII or SPI-4 ?
Wang,
This thread is is all over the place and not converging on any
resolution. With the purpose of preventing any further confusion to
those participating in P802.3ae and this reflector, I'd like to take a
stab answering your questions. I'm going to address the interface and
location you seem to imply in your note. If I am confused about the
interface location, please correct me.
Your question is which interface, the XGMII or SPI-4, will be adopted
between the link-layer and physical-layer device. For IEEE P802.3ae, the
link-layer corresponds to the OSI Data Link layer and includes the MAC
and LLC and higher layers above it. Just below the MAC, and
corresponding to the OSI Physical layer, is the Reconciliation sublayer.
P802.3ae specifies no interface between the MAC and Reconciliation
sublayer, and both are typically implemented in the same device.
P802.3ae defines the XGMII to be the interface between the
Reconciliation sublayer and the PHY. Please see P802.3ae D3.0 subclause
44.1 and Figure 44-1 for a good description of OSI layers and the
architectural positioning of 10 Gigabit Ethernet layers, sublayers and
interfaces.
Draft 3.0 is available to IEEE 802.3 voting members at:
http://grouper.ieee.org/groups/802/3/ae/private/d3.0/P802_3ae_D3_0.pdf
The 10 Gigabit Media Independent Interface (XGMII) described in Clause
46 provides an interconnection between the Media Access Control (MAC)
sublayer and Physical Layer entities (PHY). This XGMII supports 10 Gb/s
operation through its 32 bit wide transmit and receive paths. The
Reconciliation Sublayer provides a mapping between the signals provided
at the XGMII and the MAC/PLS service definition.
The 10 Gigabit Attachment Unit Interface (XAUI) described in Clause 47
provides an interconnection between two XGMII Extender sublayers to
increase the reach of the XGMII. This XAUI supports 10 Gb/s operation
through its four-lane differential-pair transmit and receive paths. The
XGXS provides a mapping between the signals provided at the XGMII and
the XAUI.
Therefore, the P802.3ae draft specifies either the XGMII and/or XAUI as
the only interfaces between what you call link-layer and physical-layer
devices. The SPI-4 interface is not appropriate for this use and has
never been presented to the 802.3ae HSSG or the P802.3ae Working Group
as an interface between the Reconciliation sublayer and the PHY. Core
proposals including the XGMII and XAUI were adopted in July, 2000. The
P802.3ae Working Group is also well past its Last New Feature Date of
November, 2000. Any movement to consider the SPI-4 interface as an
alternative to the XGMII is out of order and inappropriate at this time.
The SPI-4 interface has several flavors, the latest flavor with which
I'm familiar with is SPI-4 Phase 2. This interface is being developed by
a non-standard industry organization called the Optical Internetworking
Forum, primarily for SONET applications. SPI-4 Phase 2 is an interface
for packet and cell transfer between a Physical Layer (PHY) device and a
Link Layer device. It runs at a minimum of 10 Gbps and supports the
aggregate bandwidths
required of ATM and Packet over SONET/SDH (POS) applications. SPI-4
Phase 2 is formally specified in document oif2000.088 available to OIF
members at http://www.oiforum.com/.
For additional information about OIF interfaces, see the publicly
available white paper at:
http://www.oiforum.com/public/documents/InterfaceWhitePaper.pdf
SPI-4 Phase 2 is a much more complex, high pin count and high clock rate
interface than the XGMII. Besides 10 Gbps data busses running at 622 MHz
or higher in each direction, SPI-4 supports additional status and
control busses and associated clock signals in each data direction. Both
the XGMII and XAUI support all necessary control and status functions
necessary for 10 Gigabit Ethernet in band.
The contributors and developers of the IEEE P802.3ae standard are well
aware of the developments in other standards bodies and industry
association including SPI and SFI interfaces. Some of those interfaces,
including SPI-4, are simply not relevant and therefore have never been
proposed for consideration by the working group. Other interfaces, such
as the SFI-4 interface also known as oif00.102 have been proposed and
accepted as P802.3ae interfaces. The SFI-4 interface is the XSBI
interface intended for use as a Serial PMA interface.
I hope this clears up any confusion as to the applicability of the SPI-4
interface to the 10 Gigabit Ethernet standard.
Best Regards,
Rich
--
> Wang Wendeh wrote:
>
> Hi all,
>
> Maybe this thread has been discussed before, but I just added in this
> mailing list for a few days. Can anyone tell me which one ( XGMII or
> SPI-4) will be adopted for implementation between link-layer and
> physical-layer device? The 10G standard proposes XGMII, while it
> seems to be that vendors favor SPI-4, right? Or maybe this two
> interfaces can co-exist ??
>
> Thanks a lot!
>
> WenDeh
---------------------------------------------------------
Richard Taborek Sr. Intel Corporation
XAUI Sherpa Intel Communications Group
3101 Jay Street, Suite 110 Optical Products Group
Santa Clara, CA 95054 Santa Clara Design Center
408-496-3423 JAY1-101
Cell: 408-832-3957 mailto:rich.taborek@xxxxxxxxx
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