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RE: [802.3] A small query or clarification






-----Original Message-----
From: Anupam Singal [mailto:ASingal@xxxxxxxx]
Sent: Monday, January 06, 2003 10:21 AM
To: 'stds-802-3@xxxxxxxx'
Cc: 'stds-802-3-hssg@xxxxxxxx'; 'rtaborek@xxxxxxxxxxxxx';
'raborek@xxxxxxxxx'
Subject: [802.3] A small query or clarification 




 I have a small query if some one could address this ( I do not know where
to direct this to the right person ) :


  Relates to IEEE 802.3ae /D5.0 may 1 , 2002 clause 48 idle randomizer and
IPG management state machine .

  When I look at random integer generator logic(r) in clause  48.2.4.2 IDLE
and the figure 48-5 for 
 PCS idle randomizer I have a small question ,

  Query 1) 

  a) Is the polynomial to be implemented as x7 + x6 + 1 on a parallel 4 bit
implementation( containing 4 true data bits that
    represent this polynomial on all byte clks  on 4 bits followed by next 4
consecutive bits  of this same  polynomial for the purpose
     of loading  the a_cnt as that is 4 bits  . ( this assumes serial clk is
higher rate ) .

                 or 

  b) The x7+x6 + 1 is uses a  shift register running on byte clk itself for
all 7 terms  with 7 bits and only bits 3-0 ( ignoring rest of the bit terms
) 
       are loaded in the a_cnt ignoring the 
     (  top /  bottom ) ? ( which one ? )  3 bits from the generator
whenever a_cnt has to be loaded ?

<PAT> The intention was that one use a byte clock as one only needs to get a random bit for each idle byte. (If you ran the randomizer faster, you should still get a random enough sequence, but you would waste power.) 

<PAT> I don't understand some of what you have put in (a) as the polynomial generator will be 7 bits regardless of the rate at which it is clocked. In any case, (b) would be a typical implementation. It doesn't matter which 3 bits one uses from the generator. We are just trying to get the counter value to be random. Also, the bottom 3 bits at time x will be the top 3 bits at time x + 4 so one cannot tell externally whether you have chosen the bottom 3 bits or the top three bits.  

  Query 2)  Is a_cnt  decremented all time on data as well as  idles present
on  Xgmii or only during idles & sequences  on xgmii ?

<PAT> The behavior of A_CNT is fully described in the state machines. See 48.2.6.1.5 for the answer to your question here. It decrements once per PUDR (PMA_UNITDATA.request). That means it decrements for anything that is sent - data, idle and sequences.


   Query 3) 
       if the a_cnt becomes zero in the normal data time  for transmission
on the xgmii bus , is that again loaded with the new a_cnt or 
      is held at zero without loading  until idle appears and then loaded
again and decremented only when A is transmitted .
     
<PAT> Once again, that is defined in the state machines. once A_CNT decrements to zero, it stays there until an ||A|| is transmitted at which time a new value is loaded.

 I would appreciate if someone could respond .

  Regards ,

  Anupam Singal
  Sr Design Engineer 
  Multilink Technologies 
  asingal@xxxxxxxx
  732-537-3869