Re: 64/66 system benifits and ad-hoc agenda
Richard,
is the 64b/66b a proposal for line code in serial link, or could be
a replacement of 8b/10b
also in the Hari interface? It seems like the 8b/10b code is well
accepted as the right choice
for Hari. Is this still flexible or set in stone (because many companies
have already started
designing their high-speed I/O)?
Regards,
Kamran Azadet
Lucent
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Henning Lysdal wrote:
> Richard
>
> Thank you for getting this interesting ad-hoc started.
>
> In my opinion 64/66 is by far the most promissing of all the
> proposed line coding schemes discussed in the HSSG.
>
> Perhaps the most important feature is the ability to use existing
> OC-192 high-speed parts. This will save us all a lot of time in the
> prototype phase. Also it will allow the LAN and the WAN PHY to
> use the same hardward. ie. you can build the same module for
> both. All you need is a selectable coding scheme in the CMOS
> part (needed anyway for the HARI SerDes, assuming HARI goes
> into the standard), and a selectable reference clock for the 10.3125
> Gb/s SerDes.
>
> As I recall, the presentation you gave with Rick Walker, the work is
> almost done, so I don't imagine there will be much debate on the
> ad-hoc reflector. How do you propose we proceed with getting a
> proposal together to bring to the HSSG as soon as the standards
> process is officially started?
>
> Henning Lysdal
> GiGA A/S
>
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