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vipul.bhatt@xxxxxxxxxxx
(408)542-4113
-----Original Message-----Vipul,
From: owner-stds-802-3-hssg-serialpmd@xxxxxxxx [mailto:owner-stds-802-3-hssg-serialpmd@xxxxxxxx]On Behalf Of Geoffrey Garner
Sent: Saturday, October 21, 2000 2:36 PM
To: Vipul Bhatt
Cc: Serial PMD Ad Hoc Reflector
Subject: Re: Minutes of serial PMD specs telecon 17 Oct 00Thanks for your comments.
In SONET and SDH, the jitter tolerance would be applied at the optical input, which I believe corresponds to TP3.
GR-253 refers to the OC-N interface (which is an optical interface; it does refer separately to STS-N electrical interfaces, but
these are for lower rates, and not 10 Gbit/s). In the ITU specs, G.783 also indicates that the jitter tolerance applies to the STM-N optical interface (the specific terminology used in G.783 is the "STM-N Optical Section to Regenerator Section Adaptation Sink"; note that G.783 also covers separately STM-N electrical interfaces, but these are for lower rates). Similarly,
in SONET and SDH the jitter output would be at the optical interface, which I believe corresponds to TP2. The notion that
the jitter above 80 MHz is small applies to the optical interfaces.Consistent with the above, when SONET/SDH equipment is tested for jitter tolerance, the sinusoidal jitter is applied to the
optical interface. When jitter generation is measured, it is measured at the optical interface. These are typically the test points that are available.For deterministic jitter, I thought some more about Rohit'sn yesterday that had a short description of this. Is it correct to say
that DJ in MJS-2 is really pattern-dependent jitter (also called systematic jitter)? In SONET or SDH, this jitter arises due to
the fact that the typical output of the SONET scrambler will have runs of symbols with no transitions for various numbers of bits
(the longer the run of no transitions, the lower the probability). The overall effect is to have jitter in the recovered clock signal
due to the fact that the clock recovery circuit is going longer without getting a transition input. The effect tends to limit the clock recovery circuit bandwidth. It does seem that, if this is what is meant by DJ, it is different for 64B66B and for scrambled NRZ.I agree with your comment on the measure of jitter in the frequency domain, with one minor addition. Jitter would correspond to the power spectral density passed through the appropriate jitter measurement filter. Also, one talks of both "high-band"
jitter and "wide-band" jitter; our discussion has really been focusing on the high-band jitter. For 10 Gbit/s (STM-64) high-band
jitter, this filter is a 4 MHz, single-pole, high-pass, concatenated with an 80 MHz (this is the 80 MHz we have been talking about), 3rd order, butterworth filter. In the time-domain, I didn't fully understand your definition, but let me give you mine (tell me if it is at least clear enough that you can determine if it is the same as your definition). In the time domain, we would first look at the the phase deviation from ideal phase, as a function of time. This is the phase history, and, if we wanted to be very
precise, it is technically a discrete time random process with the discrete index referring to the respective bit in the stream and the value of the process referring to the time difference or phase difference (dependin on whether the units are units of time, rad, degrees, UI, etc.) between the actual time of that bit and the ideal time of that bit. To get jitter, we filter this phase history with
the above measurement filter. This gives the jitter history (or jitter process). The rms jitter would be the standard deviation of this random process. The peak-to-peak jitter would be the peak-to-peak of this process measured over a specified time interval (often 60 s is used).Regards,
Geoff
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