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Thanks for your comments.
I have tested a lot of jitter for electro-optic modules and line cards. Most of the jitter out of them is low frequency jitter (less than 5k). You can confirm this by reading the GR253 specs closely too, where they mention the upper cutoff is not that critical.
One of the problems in gbE spec is that there is no frequency content information. So, for instance, I do not know how much of the .7UI jitter at the receiver is due to high frequency and how much is due to low frequency. In a real life system, a lot of it is due to low frequency, as explained above. This can be easily tolerated by the CDR.
Would people be willing to change the jitter tolerance spec to xxUI for frequencies greater than yyKhz.
-----Original Message-----
From: Christensen, Benny [mailto:benny.christensen@xxxxxxxxx]
Sent: Monday, February 26, 2001 3:10 AM
To: 'Rohit Mittal'; Serial PMD Ad Hoc Reflector (E-mail) (E-mail)
Subject: RE: Jitter tolerance experiments on 2.5, 3.125 and 10 Gb/s
Hi Rohit
Comments inserted as needed for confirmation
Benny
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GIGA, an Intel company
Benny Christensen, M.Sc.E.E, Ph.D.
Mileparken 22, DK-2740 Skovlunde, Denmark
Tel: +45 7010 1062, Fax: +45 7010 1063
e-mail: benny.christensen@xxxxxxxxx, http://www.giga.dk
-----Original Message-----
From: Rohit Mittal [mailto:RMittal@xxxxxxx]
Sent: 23. februar 2001 18:02
To: 'Christensen, Benny'
Subject: RE: Jitter tolerance experiments on 2.5, 3.125 and 10 Gb/s
thanks for the info.
A question I had was this. On page 3, you mention you added white noise till
you get 1db optical power penalty. But you are using no optics. Do you put
in an electrical signal till you got , say, 1e-9 BER.
>yes. actually I'm adding (adjust) white noise to the differential data
signal in order to get the 10^-9 BER (i.e. the SNR is 15.56 dB for and ideal
theoretical decision gate, assuming gaussian noise distribution on the data
signals). So this is the SNR for the equivalent sensitivity limit of the
optical front-end.
Then you increased the electrical signal by 2db {since electrical SNR =
square (OSNR)}. So now you have no BER. Then you kept on increasing the
white noise till you again got 1e-9 BER. Am I correct?
>No. I increase the data signal by 2 dB as you write, but keeps the noise at
the constant level. So now the SNR is 17.56 dB giving a BER of lower than
10^-12 (i.e error free unless you have a long measurement gating time). But
still you will have some AM to PM noise converting to jitter (RJ) which
depends on the signal rise/fall time. Then the remaining eye opening (minus
the FF set-up + hold time) can be used for applied DJ/SJ. So if the rise
/fall is short, or noise is removed - AM-PM noise convertion is smaller,
leaving more margin for DJ/SJ.
Its an interesting note since I have been always thinking how to correlate
Sonet jitter tolerance spec with GbE/FC jitter tolerance spec. I always
suspected that the latter jitter tolerance specs were tighter than sonet
jitter tolerance spec. So a PLL which passes sonet might not pass GbE.
However, a lot of people have the misconception that sonet jitter specs are
more stringent than GbE.
>Because an optical channel normally does not have the large group delay
effect as from the electrical channel (FR4 or twisted cable)(but the
dispersion is somewhat equivalent to GD, but only dominates for L>1000 km
SMF)so the optical DJ is not significant. GbE (electrical) is much more
dominated by GD ie. ISI.
On a side note, in Sonet, the jitter tolerance curve has 2 break-points. If
you have a one-pole PLL (like the Giga PLL), then it will just slope at
-20db/decade for ALL frequecies less than its loop BW. But if you see this
PLL with a HP MTA or Omniber jitter tolerance setup, it shows flatness
from 6k to 100k. Is this an equipment limitation?
>yes I guess so. The HP clock synteziser I use, have a upper limit of around
3 UIpp jitter modulation limit below approx. 500 kHz when operating at 2.5 -
3 GHz.
Normally I use my homebuild 2.5 G clock, which uses a 38.88 MHz XO as
refrence clock, a PFC (phase/frequency detector) and have a Jpp of
(theoretical) 64 UI dependent on the PFC linearity.
-----Original Message-----
From: Christensen, Benny [mailto:benny.christensen@xxxxxxxxx]
Sent: Friday, February 23, 2001 1:50 AM
To: Serial PMD Ad Hoc Reflector (E-mail) (E-mail)
Subject: Jitter tolerance experiments on 2.5, 3.125 and 10 Gb/s
Hi all
I have made a PDF (ZIPed to 398 kB) document describing experimental Jitter
tolerance measurement on 2.5, 3.125 and 10 Gb/s CDRs. I don't know if this
will pass the reflector. (it didn't).
David Law has put in on the reflector.
THe links is:
http://grouper.ieee.org/groups/802/3/ae/public/adhoc/serial_pmd/jitter_docum
ents/jtolerance1.pdf
It also investigates the impact of different signal conditions and the
difference between ITU-T (1 dB optical receiver sensitivity penalty) and the
FC / 10 GE total jitter (TJ) specification.
The recently D2.1 changed TJ of the XAUI high frequency jitter specs to TJ
(incl SJ) of 0.7 UIpp may be difficult to fulfil for a PLL based CDR, even
under ideal signal conditions at that speed of 3.125 Gb/s.
Benny
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llllllll ii llllllll llllll
ll ll ll ll
ll llll ll ll llll llllllllll
ll ll ll ll ll ll ll
llllllll ll llllllll ll ll
GIGA, an Intel company
Benny Christensen, M.Sc.E.E, Ph.D.
Mileparken 22, DK-2740 Skovlunde, Denmark
Tel: +45 7010 1062, Fax: +45 7010 1063
e-mail: benny.christensen@xxxxxxxxx, http://www.giga.dk