RE: Jitter tolerance experiments on 2.5, 3.125 and 10 Gb/s
Hi Anthony
I'm not quite sure I can follow your arguments. So you may find my questions
and comments within the following text.
Benny
> -----Original Message-----
> From: Anthony Sanders [mailto:anthony.sanders@infineon.com]
> Sent: 1. marts 2001 10:24
> To: Christensen, Benny; Serial PMD Ad Hoc Reflector (E-mail) (E-mail)
> Subject: Re: Jitter tolerance experiments on 2.5, 3.125 and 10 Gb/s
>
>
>
> Benny,
>
> I have been starting to look at your results, and also thinking about
> your comment to response to Rohit. i.e relating Sonet jitter
> specification to Ethernet. I have been working on this problem for the
> last couple of weeks now, based on the work from Trischitta and Varma,
> "Jitter In Digital Transmission Systems".
>
> Given the theoritical meaning of 1dB signal penality for a given SJ
> jitter, one can calculate was this is in terms of clock offset for a
(to be correct: by clock offset, I guess you mean instantaneous phase/time
offset between the actual sampling point given by the clock and the middle
of the eye (crossings))
> receiver. For example the SONET specification, of 1dB for
> 0.15UI equates
> to a required maximum clock offset for a receiver of 0.25UI;
Hey I don't get this. The 1 dB is the loss in the receiver sensitivity (ie.
optical power at the connector for a BER=10^-9) due to the jitter added to
the optical signal. In order words the sensitivity drop of the receiver may
not be worse than 1 dB (optical) when then minimum 0.15 UIpp jitter
(tolerance) is added to the signal. I don't understand how you relate the
0.15 to 0.25 UI.
The 1 dB has only impact on the amplitude domain (one could say that this is
how jitter impacts are related/converted to the amplitude domain - a limit
to relative loss of sensitivity - ie. the physical linking, which is omitted
in FC, GE and XAUI stuff - primary because it is not necessary optical - OK
FC is but it may not be loss limited.)
Also when the impact is limited through this linking, one will also know how
much the BER is degraded by the maximum amount of jitter, that a TX are
allowed to generate (0.1 UIpp in 4 MHz to 80 MHz for 10 Gb/s)
=====================
I think the argumentation is wrong herefrom following.
> this means
> quite simply that the SONET specification in terms of total jitter or
> Ethernet, allows a maximum total jitter (i.e DJ + 14xRJ(RMS))
> of 0.75UI,
> (assuming no additional RJ from the receiver, which is not quite true,
> but almost).
If we use the BER=10^-9 as the reference BER, then the electrical SNR (ie.
data amplitude, which is half the swing, and the RMS noise ratio is
(theoretical gaussian white noise - no impact from physical implementation)
15.56 dB ie. 6 times. Increasing the optical power by 1 dB is equal to
increasing the SNRe by 2 dB (roughly 25 %), ie to 17.56 dB or 7.5. and the
BER now drops to less that 10^-12. (remember that these numbers and ratios
are amplitude not pp swing)
The AM-PM noise conversion rate is dependent on the slope of the data
signals: Ideal 0 ps rise/fall gives no jitter. However, a physical
implementation (WC sinusoidal or what is obtained by the SDH filters) will
have 20-80% rise / fall of say 0.3 UI (ie 30 ps for a 10 G signal or 120 ps
for a 2.5 G). From the linear slope of the transition one can roughly
estimate the RJ(rms) stemming from the AM noise. ie. 0.3/(80%-20%) *1 /2/
7.5 = 0.033 UIrms (still gaussian).
Now, increasing the TOTAL jitter pp (ie. converted noiseRJ + SI), which
recovers the BER=10^-9, means that noise contributes with the RJpp(at 10^-9
confidence level ie. 2*6*rms value) = 2*6*0.033 UI = 0.4 UIpp to the total
jitter. What is left for SJ is simply the CDR 0.7 UIpp max limit - the 0.4
UIpp (PM noise RJ).
I can see that the numbers are a little off target (but this was only meant
to be a rough estimation - not to far from reallty I guess.)
>
> (clock offset = deviation of the sampling clock from the
> ideal center of
> the data eye given symetrical noise distributions)
>
> The impact would be, that for the 3.125Gbps Demux you have
> measured; if
> you see a 1dB penality at 0.65U of SJ, for example, the clock
> offset of
> the device is a lot better than 0.35UI (exact number I have to calc
> today, I didnīt calculate this number for such high SJ), I
> send this out
> when I finished writting the Annex 48B.
>
> I would be interested in hearing if you are of the same opinion.
I not sure I will commit to that, as the I feel the assumptions made above
is not correct (in my opinion)
Benny
>
> Best regards,
>
> Anthony Sanders
> Principal Engineer
> Infineon Technologies
> Munich, Germany
>
>
>
> "Christensen, Benny" wrote:
> >
> > Hi Rohit
> >
> > Comments inserted as needed for confirmation
> >
> > Benny
> > --------------------------------------------
> > llllllll ii llllllll llllll
> > ll ll ll ll
> > ll llll ll ll llll llllllllll
> > ll ll ll ll ll ll ll
> > llllllll ll llllllll ll ll
> >
> > GIGA, an Intel company
> > Benny Christensen, M.Sc.E.E, Ph.D.
> > Mileparken 22, DK-2740 Skovlunde, Denmark
> > Tel: +45 7010 1062, Fax: +45 7010 1063
> > e-mail: benny.christensen@intel.com, http://www.giga.dk
> >
> > -----Original Message-----
> > From: Rohit Mittal [mailto:RMittal@oni.com]
> > Sent: 23. februar 2001 18:02
> > To: 'Christensen, Benny'
> > Subject: RE: Jitter tolerance experiments on 2.5, 3.125 and 10 Gb/s
> >
> > thanks for the info.
> >
> > A question I had was this. On page 3, you mention you added
> white noise till
> > you get 1db optical power penalty. But you are using no
> optics. Do you put
> > in an electrical signal till you got , say, 1e-9 BER.
> >
> > >yes. actually I'm adding (adjust) white noise to the
> differential data
> > signal in order to get the 10^-9 BER (i.e. the SNR is 15.56
> dB for and ideal
> > theoretical decision gate, assuming gaussian noise
> distribution on the data
> > signals). So this is the SNR for the equivalent sensitivity
> limit of the
> > optical front-end.
> >
> > Then you increased the electrical signal by 2db {since
> electrical SNR =
> > square (OSNR)}. So now you have no BER. Then you kept on
> increasing the
> > white noise till you again got 1e-9 BER. Am I correct?
> >
> > >No. I increase the data signal by 2 dB as you write, but
> keeps the noise at
> > the constant level. So now the SNR is 17.56 dB giving a BER
> of lower than
> > 10^-12 (i.e error free unless you have a long measurement
> gating time). But
> > still you will have some AM to PM noise converting to
> jitter (RJ) which
> > depends on the signal rise/fall time. Then the remaining
> eye opening (minus
> > the FF set-up + hold time) can be used for applied DJ/SJ.
> So if the rise
> > /fall is short, or noise is removed - AM-PM noise
> convertion is smaller,
> > leaving more margin for DJ/SJ.
> >
> > Its an interesting note since I have been always thinking
> how to correlate
> > Sonet jitter tolerance spec with GbE/FC jitter tolerance
> spec. I always
> > suspected that the latter jitter tolerance specs were
> tighter than sonet
> > jitter tolerance spec. So a PLL which passes sonet might
> not pass GbE.
> > However, a lot of people have the misconception that sonet
> jitter specs are
> > more stringent than GbE.
> >
> > >Because an optical channel normally does not have the
> large group delay
> > effect as from the electrical channel (FR4 or twisted
> cable)(but the
> > dispersion is somewhat equivalent to GD, but only dominates
> for L>1000 km
> > SMF)so the optical DJ is not significant. GbE (electrical)
> is much more
> > dominated by GD ie. ISI.
> >
> > On a side note, in Sonet, the jitter tolerance curve has 2
> break-points. If
> > you have a one-pole PLL (like the Giga PLL), then it will
> just slope at
> > -20db/decade for ALL frequecies less than its loop BW. But
> if you see this
> > PLL with a HP MTA or Omniber jitter tolerance setup, it
> shows flatness
> > from 6k to 100k. Is this an equipment limitation?
> >
> > >yes I guess so. The HP clock synteziser I use, have a
> upper limit of around
> > 3 UIpp jitter modulation limit below approx. 500 kHz when
> operating at 2.5 -
> > 3 GHz.
> >
> > Normally I use my homebuild 2.5 G clock, which uses a 38.88
> MHz XO as
> > refrence clock, a PFC (phase/frequency detector) and have a Jpp of
> > (theoretical) 64 UI dependent on the PFC linearity.
> >
> > -----Original Message-----
> > From: Christensen, Benny [mailto:benny.christensen@intel.com]
> > Sent: Friday, February 23, 2001 1:50 AM
> > To: Serial PMD Ad Hoc Reflector (E-mail) (E-mail)
> > Subject: Jitter tolerance experiments on 2.5, 3.125 and 10 Gb/s
> >
> > Hi all
> >
> > I have made a PDF (ZIPed to 398 kB) document describing
> experimental Jitter
> > tolerance measurement on 2.5, 3.125 and 10 Gb/s CDRs. I
> don't know if this
> > will pass the reflector. (it didn't).
> > David Law has put in on the reflector.
> > THe links is:
> >
> http://grouper.ieee.org/groups/802/3/ae/public/adhoc/serial_pm
d/jitter_docum
>
> ents/jtolerance1.pdf
> It also investigates the impact of different signal conditions and the
> difference between ITU-T (1 dB optical receiver sensitivity penalty) and
the
>
> FC / 10 GE total jitter (TJ) specification.
>
> The recently D2.1 changed TJ of the XAUI high frequency jitter specs to TJ
> (incl SJ) of 0.7 UIpp may be difficult to fulfil for a PLL based CDR, even
> under ideal signal conditions at that speed of 3.125 Gb/s.
>
> Benny
> --------------------------------------------
> llllllll ii llllllll llllll
> ll ll ll ll
> ll llll ll ll llll llllllllll
> ll ll ll ll ll ll ll
> llllllll ll llllllll ll ll
> GIGA, an Intel company
> Benny Christensen, M.Sc.E.E, Ph.D.
> Mileparken 22, DK-2740 Skovlunde, Denmark
> Tel: +45 7010 1062, Fax: +45 7010 1063
> e-mail: benny.christensen@intel.com, http://www.giga.dk