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RE: SJTP: Minutes from today's call




Ben (and others),

My 2 cents on the test pattern issue:
- the test pattern, as I understand it, is intended to test the PMA/PMD and does nothing for the PCS/WIS;
- the PMA/PMD are common between LAN and WAN PHY;
- if A1/A2 sequences are indeed more stressful, why is it not being used in the LAN test pattern as well? I don't see anything in the standard that would allow an implementer to relax PMA/PMD parameters when a LAN-only PHY is being created;
- therefore, I don't understand why we should have different test patterns for LAN and WAN cases.

Further:
- the WAN-PHY has a bypass mode specified, whereby the output of the 64B/66B PCS can be directly passed to the XSBI;
- therefore, if a common test pattern can be created and specified in Clause 49, and allowed to be operative in both LAN-PHY and WAN-PHY (bypass) modes, no further changes to the spec are needed;
- it would be preferable if this test pattern included stressful conditions such as A1/A2 sequences, for both LAN and WAN cases;
- therefore, I would prefer to see option #3 of your e-mail adopted, possibly with modifications to the pattern as mentioned, as this seems to result in the lowest compliance overhead for implementers while still preserving the notion of an integral jitter test facility in the PHY.

An informative note referencing the ITU jitter test pattern might be of use to implementers. However, I would not be in favor of making this mandatory (thus creating two and possibly three different test patterns within 10G Ethernet); in this case, though, as we're going to specify a jitter test pattern anyway, a reference to the ITU pattern might only serve to confuse people.

Cheers,

- Tom Alexander

-----Original Message-----
From: Ben Brown [mailto:bbrown@amcc.com]
Sent: Tuesday, April 17, 2001 2:38 PM
To: serialpmd; Tom Alexander; Paul Bottorff; David Martin; Norival Figueira
Subject: SJTP: Minutes from today's call


Hello,

Attached are the minutes from today's Serial Jitter Test Pattern
phone call. Thanks to all attendees and a reminder that next
week's phone call is on for the same time and you should be
able to use the same number (listed at the bottom of the
minutes).

Tom, David, Paul, Norival, others with WIS/SONET experience:

The focus of today's discussion was around a test pattern for
the WAN PHY. As (hopefully) you can see in the minutes, we
talked about 4 specific options:

1) No modifications to the WIS, use the LAN pattern as the
   WIS payload

2) Use the A1/A2 pattern for framing with no other overhead
   bytes and do not restrict the frame duration to 125 usec

3) Use the LAN pattern directly, in a similar fashion to what
   is currently defined in D3.0 (i.e., no A1/A2 framing)

4) Do nothing and inform WIS implementors about the pattern
   specified in ITU-T G.957 (as described in the minutes and
   the attached email from Piers Dawe - CID_pattern).

The advantages of #1 are obvious as the standard doesn't need
to change. However, the problem is with the synchronization
process. If there is a feature in the pattern that causes the
PLL to drop sync consistently on every frame, the sync process
will never get around to sending payload to the PCS for
analysis. But then again, if the PLL can't maintain sync, do
we care?

The other disadvantage is that the pattern is very long for
BERT memory. You can either send the same pattern in every
frame, which probably fits into a BERT, but this does not
contain an integral multiple of 66-bit blocks so a receiving
PCS would lose sync on every SONET frame. You could also send
a pattern which repeats with an integral number of 66-bit
blocks but this requires almost 200,000 66-bit blocks over
exactly 11 SONET frames. This works well in a loopback or
PHY to PHY test but does not fit well in BERT memory.

#2 requires changes to the WIS and may affect implementations
regarding how they pass "payload" between the PCS and the WIS.
This would fix the problem of allowing the pattern to both
fit inside a BERT and be passed to the PCS without loss of sync.

#3 eliminates the A1/A2 pattern which itself is a rather
stressful pattern that should probably not be eliminated from
a WAN PHY test pattern.

#4 has been around for a long time without (public) modification.
This either means it works adequately or has been replaced with
proprietary solutions. Choosing this option has the advantage
(for this ad hoc) that our work becomes focused on the serial
LAN only. However, is this pattern sufficient to guarantee
interoperability? Should we make it mandatory when SONET has
made it optional?

We're very interested in the opinions of people with experience
in this area regarding what other ramifications exist that we
haven't even considered. Your input, or that of anyone else for
that matter, would be greatly appreciated. I'm sure we'll be
discussing this in the next phone call but an email dialog would
be a great way to get some progress out of the way.

Thanks,
Ben

--
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Benjamin Brown
AMCC
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