RE: XAUI electrical status
Patterns are being defined for jitter measurements, but no patterns are
specified for verifying driver compliance using the eyes of fig's 47-4 or
47-7. I believe the assumption has been K28.5 +/-, but this isn't explicit.
Perhaps it should be, or perhaps some other data pattern is more
appropriate. I'm fishing for input in the form of comments and proposals to
D3.0.
-Dawson
-----Original Message-----
From: Boaz Shahar [mailto:boazs@mysticom.com]
Sent: Thursday, April 19, 2001 2:18 AM
To: 'Kesling, Dawson W'; Serial PMD reflector (E-mail)
Subject: RE: XAUI electrical status
Dawson,
>
> Driver compliance eyes
> - Data pattern is not defined.
Are we looking for patterns additional to CJPAT and CRPAT defined in
Appendix 48A? May be it is better to update them instead.
Thx.,
Boaz
> -----Original Message-----
> From: Kesling, Dawson W [mailto:dawson.w.kesling@intel.com]
> Sent: Wednesday, April 18, 2001 6:21 PM
> To: Serial PMD reflector (E-mail)
> Subject: XAUI electrical status
>
>
>
> Work on XAUI electrical issues has been proceeding in several
> quarters, but
> with little public discussion of late. Following is a summary of XAUI
> electrical issues to spur both proposals on D3.0 and further work in
> preparation for the Interim next month. Jitter specific
> issues are being
> tracked separately by Anthony and are not listed here.
>
> Compliance channel phase response
> (See
> http://grouper.ieee.org/groups/802/3/ae/public/adhoc/serial_pm
> d/xaui_documen
> ts/XAUI_mar01_agenda.pdf page 8.)
> - Please consider whether a phase specification is really
> needed for driver
> compliance.
>
> Return loss
> (See
> http://grouper.ieee.org/groups/802/3/ae/public/adhoc/serial_pm
> d/xaui_documen
> ts/XAUI_mar01_agenda.pdf page 9.)
> - Measurements in progress by Ishwar.
> - Additional chip measurements would be useful.
> - Definitive analysis presentation needed to determine
> acceptable limits
> with respect to system performance
>
> Vmax
> (See
> http://grouper.ieee.org/groups/802/3/ae/public/adhoc/serial_pm
> d/xaui_documen
> ts/XAUI_mar01_agenda.pdf page 10.)
> - Solution proposals needed.
>
> Crosstalk
> (See
> http://grouper.ieee.org/groups/802/3/ae/public/adhoc/serial_pm
> d/xaui_documen
> ts/XAUI_mar01_agenda.pdf page 11.)
> - Study being done by John D.
> - Additional issue: The far end eye of Fig. 47-4 is used to
> define both
> driver compliance (47.3.3.5) and the valid receive signal
> (47.3.4.1). There
> is no difference in vertical eye opening to account for
> crosstalk in the
> receive case.
>
> Compliance channel low frequency spec limit
> - Technical opinions welcome concerning how low in frequency
> the compliance
> channel spec should cover.
>
> Driver compliance eyes
> - Data pattern is not defined.
> - D3.0 allows using either a system clock or a golden PLL for
> eye trigger,
> but eye results will differ with some data patterns.
>
> Please review and resubmit relevant XAUI comments on D2.1 which were
> deferred to D3.0:
> http://grouper.ieee.org/groups/802/3/ae/comments/d2.1/index.html
>
> Thank you all.
> -Dawson Kesling
> Editor, Clause 47
>