Re: SJTP: WIS Pointer Processor
Tim,
For the LAN pattern, we chose to use a particular starting point
for the scrambler in order to guarantee that over the very long
scrambler pattern we could select the appropriate, very small
subset.
For the WAN pattern, this is not the case. Your proposal already
suggests we're using 29% of the total PRBS but we're complicating
the process by starting the PRBS at a defined location on every
other SONET frame.
I'm being told by AMCC internal sources that BERTs exist which
are able to synchronize to the SONET frame then synchronize to
a PRBS within the payload area of that frame. If this is the
case, why can't we simply let the PRBS run from any known
starting location? It would simplify the generation of the
payload in regards to timing it to the SONET frame. It would
also no longer require ignoring a group of errors at the start
of every other frame.
Thanks,
Ben
Tim Warland wrote:
>
> Ben was correct. The H1H2 pointer value of 522 corresponds to
> the POH starting at the top of the SONET frame immediately
> after the Z0 byte locations (refer to G.253 figure 3-38).
>
> This alignment changes the proposal I had submitted for the
> WIS jitter test pattern in which I had assumed the SPE started
> near the middle of the frame. With this new view on alignment,
> the impact of the CID pattern is now reflected on the J1 byte.
> (Given that a CID can cause transmitter eye closure, or receiver
> CDR drift this effect can be measured by the data stream
> at the conclusion of the CID).
>
> In order to maintain the effectiveness of CID stress for WIS
> compliant PMDs, it will be necessary to program the J1 byte
> to a value which has an impact on CID susceptible components.
> Fortunately, the J1 byte is already defined to be programmable.
>
> It is now necessary that we fix the value of J1 (just as we
> must provide fixed values for all overhead bytes for the pattern
> test to be successful).
>
> This benefits the testers since now they can perform two
> independent tests from the same pattern. The first being
> the CID test with analysis only on the received value of
> J1. The second being sensitivity type tests in which the
> SNR (etc) is decreased until a BER passes a threshold.
> For this type of test the CID is ignored and the PRBS
> is the focus.
>
> Several things still have to happen. If there are no exceptions
> to this proposed change, I shall update the WIS Jitter Test
> Patterns document to reflect the impact of J1. We need input
> from PMD people to determine the start pattern for the
> PRBS (not all zero), and a value for J1. Finally, all programmable
> OH bytes must be asigned a fixed value.
>
> --
> Tim Warland P.Eng.
> Hardware Design Engineer Broadband Products
> High Performance Optical Component Solutions
> Nortel Networks (613)765-6634
--
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Benjamin Brown
AMCC
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Suite 104
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bbrown@amcc.com
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