| Thread Links | Date Links | ||||
|---|---|---|---|---|---|
| Thread Prev | Thread Next | Thread Index | Date Prev | Date Next | Date Index |
|
Please pull comment 81 from the EZ bucket. Task force needs to consider what the proper timing should be (commenter wasn’t sure). Comment shown below for clarity: Cl 104 SC 104.7.3.3 P 61 L 35 # 81 Comment Type TR "The master device shall initiate a read time slot by pulling VPSE low and then pulling-up VPSE within tW1L. This is exactly the same language as generating a Write 1 timeslot, making the read time slot and the write 1 timeslot not uniquely identifiable. Additionally, there is a timing problem, because according to this tW1L can be between 0.09 ms and 0.33 ms, while the master may sample anytime between 0.27ms and 0.33ms, meaning that if the slave hasn't recognized tW1L until near the end of its allowed duration, it won't have asserted data. The original spec seems to have had a separate tRL, which was slightly shorter than tW1L, and figure 104-15 shows the tW1L expiring before the tMSR. Recommend reinstating tRL as a shorter duration than tMSR min." SuggestedRemedy "Change ""tW1L"" to ""tRL"", both on P61 L35 and in Figure 104-15. Add tRL to Table 104- 7, with a range of 0.09 ms to 0.25 ms (not exactly sure on the max time, but it has to be less than 0.27ms with some margin). Adjust PICS SCCP14 to reference tRL." PROPOSED ACCEPT IN PRINCIPLE. EZ. PICS editor granted license to adjsut SCCP14 to reference tRL. George A. Zimmerman, Ph.D. President & Principle Consultant CME Consulting, Inc. Experts in PHYsical Layer Communications 1-310-920-3860 From: Dan Dove [mailto:dan.dove@xxxxxxxxxxxxxxxxxx]
Dear Colleagues, |