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All, As we discuss potential market fragmentation for 25GBASE-CR PHYs based upon reach (CR-S, CR-L, etc)... We should also keep in mind that MMF optics will require RS-FEC. So, if we choose to create a PHY type that does not support RS-FEC, we are not just dividing it from the relatively small 3-5m copper market. (I assume its small relative to 0-3m market) but we are also dividing it away from the larger body of 100G devices that would break out into 4x25G devices, and dividing it away from 25G MMF devices which may have a reasonable market size. There was a comment made in today's adhoc that plug-and-play leads to happy customers. I would take it one step further, plug-and-play leads to more rapid market adoption and conversely, lack of plug-and-play can lead to substantial market disruption. Historically, standards that have had trouble getting off the ground due to interoperability problems, lagged and sometimes never gained market acceptance. In some cases, MSAs or other means were used to achieve the desired customer satisfaction. We could literally "snake-bite" the standard in customer's eyes if we don't have plug-and-play, or at least clearly defined PHYs so that customers don't attempt to gain interoperability where it's not intended. I believe we should take all of this into account when making our decision on which way to proceed and am willing to collaborate on a presentation to this effect if someone wishes to join me. I don't have a conclusion at this point, but am leaning toward a single PHY with both FECs and the ability to disable FEC for low-latency applications. This leaning comes from the data presented by Jeff Slavik combined with comments that in a typical ASIC the overall impact of the PHY gate counts for RS-FEC will be relatively small. I also agree with Eric's idea of remapping priority for low-latency vs cable-reach to ease Auto Negotiation, but would prefer to see it simply CR vs CR w/o FEC. I base this on the idea that only those who are engineering links would disable FEC. |