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There are 3 sublayers that have to support deep sleep: the PCS+RS, BASE-R FEC and 25G RS-FEC. Theoretically these could be three separate IPs. The PCS+RS must
support deep sleep for any mode, but the other two may or may not support it. So, from silicon point of view it makes sense to separate advertisement (and if we do, then surely someone would eventually use it…). However I am not sure
whether it makes business sense, and whether there is any impact if we use only one advertisement bit and require support of all implemented FEC modes – I think this would follow the KISS principle. </Adee> From: Brad Booth [mailto:bbooth@xxxxxxxx]
Jeff, The confusion I have is we autoneg the technology ability for 25G no FEC, KR-FEC and RS-FEC, but also then do it for deep sleep for each of the technology abilities. What I'm trying to understand is if deep sleep needs to be dependent on
each technology ability. In other words, would a PHY advertise all three FEC options, but then only advertise one technology ability is capable of deep sleep. My thought was advertising deep sleep ability would indicate that it applies to all the 25G technologies
the PHY is able to support. I don't care one way or the other, but as a former silicon guy, it just seemed strange to me to design multiple 25G modes in a PHY and then not apply deep sleep (if supported) across all those modes. Thanks, Brad On Fri, Aug 14, 2015 at 9:20 AM, Jeff Slavick <jeff.slavick@xxxxxxxxxxxxx> wrote: Arg. Confusing 45.2.7.13 (AN) and 45.2.1.14 (PMA/PMD) In 45.2.1.4 we have all 4 PHY types. In 45.2.7.13 we have the combined advertisement of R and R-S. So we've done the proper thing so far, in that we've combined them during AN, but listed them explicitly in PMA section. My musing over whether it should be 3b during AN (and in PMA/PMD) still holds true though. -Jeff On Fri, Aug 14, 2015 at 11:42 AM, Jeff Slavick <jeff.slavick@xxxxxxxxxxxxx> wrote: Hi Brad, At the very least we I think should reduce the bits to 25GBASE-xR and 25GBASE-xR-S ability bits. We only advertise those two during AN, so no need to have independent bits for backplane and cables in EEE as well. I could see setting
only the -S bit happening when a PHY supports deep sleep for 10G speed up, but not RS-FEC operation. Which then begs whether it should be 3 capability bits based on operating mode of the 25G PHY: 25G 64b/66b deep sleep, 25G BASE-R FEC deep sleep, 25G RS-FEC deep sleep. -Jeff On Mon, Aug 10, 2015 at 4:10 PM, Brad Booth <bbooth@xxxxxxxx> wrote: I was in the process of reviewing the draft and noticed that in 45.2.7.13 and 14 that we're exchanging the ability to support deep sleep for 25G, but that we separate out the advertisement/ability based upon KR/CR and KR-S/CR-S. Is it really necessary to separate them? Would someone build a PHY that does KR and KR-S but only provide deep sleep for one of the operating modes? The reason I'm asking is that we're burning through the last two bits in register 7.61 at the same time folks are talking about doing a 50G project. Any thoughts or feedback on that? I'm willing to submit a comment on it, but I thought I'd gauge the sense of the reflector first. Thanks, |