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All, Just a reminder of tomorrow’s logic ad hoc meeting (8am PDT), the agenda is: A 400GbE PCS Option – Mark Gustlin 400GbE PCS Direct Coding Analysis - Haoyu Song Error performance objective for 400GbE – Pete Anslow The invite with the WebEx information has been previously sent out, please let me know if you do not have the invite and want to attend. Regards, Mark Gustlin From: Mark Gustlin [mailto:mark.gustlin@xxxxxxxxxx]
All, This email is to announce the next 400Gb/s Ethernet Study Group Logic ad hoc conference call. The stated charter is: Evaluate 400GbE architecture implementations to make recommendations regarding possible objectives. The study group has adopted many of the logic related objectives in previous study group meetings, but we have yet to adopt an objective on BER or FLR. Priority therefore will be given to presentations addressing a possible BER or FLR
objective. The call is set for 8:00am Pacific on Wednesday 10/23/2013, lasting up to 2 hours if we receive sufficient presentation material. If you are interested in presenting, please request a timeslot by 10/21. A calendar invite with WebEx information will be sent shortly. Since this is an official Ad hoc meeting of the study group, please familiarize yourself with the meeting guidelines before the meeting; they can be found here: https://development.standards.ieee.org/myproject/Public/mytools/mob/preparslides.pdf Also please no restrictive notices in the presentations. Please remember to mute yourself unless you are speaking, or the host will do it for you if there is noise or echo from your line. Regards, Mark Gustlin
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