[802.3_400G] Chip-to-Module electrical Channel Data Available

["John D'Ambrosia" <John_DAmbrosia@xxxxxxxx>]

All,

Megha Shanbhag and Nathan Tracy have provided Channel Model data for 50Gb/s chip to module analysis. 

 

The following is an excerpt from their summary presentation (http://www.ieee802.org/3/bs/public/channel/TEC/shanbhag_3bs_14_0623.pdf) that describes the provided data –

 

·         TE has contributed two chip to module channel models to the OIF for analysis as part of the 56G VSR project. We are providing the same channel models to the IEEE for analysis and feedback as 50G channel development occurs across the industry.

·         Due to the importance of the IEEE’s 802.3bs project, We are contributing two S-parameter models for use by IEEE attendees.

·         Channel models:

o    “Next generation 28Gb/s high density SMT IO”

o    “Next generation 28Gb/s press-fit stacked IO”

·         These channels include module connector concepts that are being evaluated for 28Gb/s applications. These are NOT existing connectors and they have been designed for 28Gb/s applications. This is a good time for feedback.

 

This channel data will be useful for the upcoming meeting in July for potential proposals for the chip-to-module electrical interfaces.  

 

I would like to thank Megha and Nathan for their contribution in helping to move the project forward.

 

Regards,

 

John D’Ambrosia

Chair, IEEE P802.3bs 400GbE Task Force