Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

Re: [STDS-802-3-400G] Follow up to IEEE P802.3bs 400 Gb/s Ethernet SMF Ad Hoc conference call



Peter,

Thanks for the clarification. It is sufficient.

 

On the exotic thing, I can provide a little more detail into the (simulation) work I’ve done. It uses only linear techniques, basically some (very) mild peaking in the transmitter output and a three stage linear equalizer integrated into the TIA. I’ve found that such linear techniques are sufficient for the systems I am modeling, as they have decent bandwidth and a relatively low order response (unlike copper PAM links, which can have very complex/high order responses). As I showed in Ottawa no DAC is required, and the decoder is done with a multi-level slicer approach. However other implementations could require more complexity in the electronics (ie, if you have a low bandwidth, high order TIA).

 

I think the horizontal vs. vertical eye opening question is a good one, as PAM signaling creates a penalty in both directions. My experience is the vertical penalty tends to be larger than the horizontal penalty (I presented some info on this in San Diego), as an example the results I showed in Ottawa had a 4.8 dB vertical penalty due to the PAM signaling, but only about 2dB of horizontal penalty (measured compared to an NRZ mode of operation). As stated above, this may not always be the case though, and is dependent on the component BW.

 

Thanks,

Brian

 

From: Peter Stassar [mailto:Peter.Stassar@xxxxxxxxxx]
Sent: Wednesday, October 01, 2014 9:13 AM
To: Brian Welch
Cc: STDS-802-3-400G@xxxxxxxxxxxxxxxxx
Subject: RE: [STDS-802-3-400G] Follow up to IEEE P802.3bs 400 Gb/s Ethernet SMF Ad Hoc conference call

 

Hi Brian,


Thanks for the questions.

Regarding the “exotic” I was not so much referring to optical technology, but rather electronic DSP, FEC, ADC, DAC, FFE, DFE technology. If the electronic “processing” will be significant then probably large, “hot” asic technology will be needed inside optical modules, which for obvious reasons is not desirable.

 

Regarding the additional questions “Furthermore I suggest to add Tx eye diagrams to all inputs and investigate the effect of jitter to this”, these are in fact 2 questions:

1.       Add Transmitter eye diagrams to the test results: this will give some information on how open the eye is, either in the horizontal (time) or vertical (amplitude) directin

2.       Investigate the effect of jitter to this: well if the horizontal eye opening is small, then adding a bit of jitter will close the eye completely, which also is not desirable.

 

Is this sufficient clarification?

 

Kind regards,

 

Peter

 

Peter Stassar, 施笪安

Technical Director, 术总监

Huawei Technologies Ltd, 华为技术有限公司

European Research Center, 欧洲研究所

Karspeldreef 4, 1101CJ Amsterdam

The Netherlands

Tel: +31 20 4300 832

Mob: +31 6 21146286

 

From: Brian Welch [mailto:bwelch@xxxxxxxxxxx]
Sent: Wednesday, October 01, 2014 6:03 PM
To: Peter Stassar; STDS-802-3-400G@xxxxxxxxxxxxxxxxx
Subject: RE: [STDS-802-3-400G] Follow up to IEEE P802.3bs 400 Gb/s Ethernet SMF Ad Hoc conference call

 

Peter,

On the second bullet, I think it depends on what your definition of ‘exotic’ is. I’ve been using silicon photonics optical I/O’s with TX bandwidth varied between 25-30G, with minimal ISI, running PRBS31 (of course, as mentioned in Ottawa, these are simulations, not yet in hardware). I don’t consider it exotic, as it’s essentially the same technology that we use for 40G and 100G, but it’s a matter of perspective.

 

On your additional questions, I’m not sure I understand “Furthermore I suggest to add Tx eye diagrams to all inputs and investigate the effect of jitter to this.” Could you elaborate at all?

 

Thanks,

Brian

 

 

From: Peter Stassar [mailto:Peter.Stassar@xxxxxxxxxx]
Sent: Wednesday, October 01, 2014 8:40 AM
To: STDS-802-3-400G@xxxxxxxxxxxxxxxxx
Subject: [STDS-802-3-400G] Follow up to IEEE P802.3bs 400 Gb/s Ethernet SMF Ad Hoc conference call

 

Dear all,

 

During yesterday’s SMF ad hoc conference call I presented http://www.ieee802.org/3/bs/public/adhoc/smf/14_09_30/stassar_01_0914_smf.pdf.

 

This presentation contained some questions to all for follow-up.

The most important were:

         Identify a working assumption for reasonable transmitter output power: in my presentation I mentioned -1.5dBm as a realistically minimum average transmitter output power before the mux, but comments were made that this value is too low. The value of -1.5dBm however was intended for a TDP value of 1 dB. In the case of a TDP of 3 dB that minimum value could go up to +0.5 dBm, at least in the case of the power budget example contained in my presentation. So I would appreciate inputs on not only a realistic minimum value, but also a realistic range (thus upper value).

         Can we sufficiently minimize ISI with PAM4 transmitters or will it require exotic technology? This question is intended to jointly investigate the source of the (potential) BER-floor seen in most experiments with PAM4. I believe addressing this question will be essential if we would like to use the PAM4 modulation format. For these experiments I suggested to use SSPR patterns instead of the shorter PRBS15 patterns. Of course PRBS31 will be OK as well.

 

Additional questions, related to the previous issue:

         Related to the BER-floor question, we may want to investigate this issue while varying the bitrate, perhaps even for 10Gb/s, 25Gb/s, 50Gb/s and 100Gb/s.

         During the experiments it will be very useful which parameters will move the BER floor up and down.

         Furthermore I suggest to add Tx eye diagrams to all inputs and investigate the effect of jitter to this.

 

Finally I would appreciate any further questions, comments and/or suggestions to my presentation.

 

Thanks in advance.

I am looking forward to continue our constructive debate during the next SMF ad hoc call on Tuesday 14 October.

 

Kind regards,

 

Peter

 

Peter Stassar, 施笪安

Technical Director, 术总监

Huawei Technologies Ltd, 华为技术有限公司

European Research Center, 欧洲研究所

Karspeldreef 4, 1101CJ Amsterdam

The Netherlands

Tel: +31 20 4300 832

Mob: +31 6 21146286