Sorry I missed Monday’s call. Whatever we do for the pattern generator “initial jitter settings” the final values will need to be adjusted to provide the required
eye width at the calibration point using the calibration procedure that should be the same as is used for measuring the C2M Tx output eye width. (The method of doing the adjustment will have to be defined, but is adjusting the Rj for CAUI4 and I’d suggest
we do the same for CDAUI8). See the following from 83E.4.1.1
Eye height and eye width, extrapolated to a probability of 10-15, are then measured at TP1a based on the
eye measurement methodology given in 83E.4.2.
Random jitter and the pattern generator output amplitude are adjusted (without exceeding the differential pk-pk input voltage tolerance specification as shown in Table 83E–7) to result in the eye height and eye width given in Table 83E–8 using the reference
receiver with the setting of the CTLE that maximizes the product of eye height and eye width.
My preference for the initial jitter settings is that we would use the same method and values as we use to define the Chip to Chip CDAUI8. In Draft 1.1 that
is Dj and Rj of “clock jitter” plus EOJ, but there have been proposals to change that and I think that C2M should follow the decisions for chip to chip CDAUI8.
So I’m saying the first option for the final calibration result, but the 2nd option for the initial jitter settings. The reasons that there needs
to be two different measurements is that the stressed sensitivity input should match the eye width allowed for a worst case Tx. However the pattern generator output will have a different amount of jitter because of reflections and crosstalk injection between
the pattern generator output and the calibration point (which will obviously vary from one test set-up to another.).
Mike Dudek
QLogic Corporation
Director Signal Integrity
26650 Aliso Viejo Parkway
Aliso Viejo CA 92656
949 389 6269 - office.
Mike.Dudek@xxxxxxxxxx
From: Mellitz, Richard [mailto:richard.mellitz@xxxxxxxxx]
Sent: Wednesday, February 03, 2016 10:03 AM
To: STDS-802-3-400G@xxxxxxxxxxxxxxxxx
Subject: Re: [STDS-802-3-400G] Electrical Ad Hoc email straw poll on Annex 120E (C2M) Pattern generator characteristics tables
From: Andre Szczepanek [mailto:aszczepanek@xxxxxxxxx]
Sent: Wednesday, February 03, 2016 5:16 AM
To: STDS-802-3-400G@xxxxxxxxxxxxxxxxx
Subject: [STDS-802-3-400G] Electrical Ad Hoc email straw poll on Annex 120E (C2M) Pattern generator characteristics tables
In Monday’s Electrical ad hoc I proposed two alternative solutions to resolving the Pattern Generator Characteristics table TBDs (see snapshot of
slide below).
These tables define the pattern generator jitter used in the Host & Module stressed input test procedures.
The first proposal uses a CAUI-4 C2M like definition of pattern generator jitter.
The second proposal uses CDAUI-8 C2C TP0a like definition of pattern generator (clock) jitter. CEI-56-VSR-PAM4 uses such a definition.
-
Although I have called out the 94.3.12.6.1 measurement method, the intention is “use CDAUI-8 C2C measurement method”.
The scope of this straw poll is not the specific table values, just the definition method:
Electrical ad hoc Straw Poll
I support a CAUI-4 C2M like definition of pattern generator jitter for the Host & Module stressed input test procedures ____
I support a CDAUI-8 C2C TP0a like definition of pattern generator (clock) jitter for the Host & Module stressed input test procedures _x___
Please respond by EOD Sunday so I can present the results at Monday’s electrical ad hoc.
Regards
Andre Szczepanek (P802.3bs 400 Gb/s Ethernet Task Force Electrical Ad Hoc chair)
